MicroBlaze features a debug interface to support JTAG based software debugging tools (commonly known as BDM or Background Debug Mode debuggers) like the System Debugger (XSDB) tool. The debug interface is designed to be connected to the MicroBlaze Debug Module (MDM) core, which interfaces with the JTAG port of FPGAs. Multiple MicroBlaze instances can be interfaced with a single MDM to enable multiprocessor debugging.
To be able to download programs, set software breakpoints and disassemble code, the instruction and data memory ranges must overlap, and use the same physical memory.
Debug registers are accessed using the debug interface, and are not directly
visible to software running on the processor, unless the MDM is configured to enable
software access to user-accessible debug registers. The debug interface can either use
JTAG serial access or AXI4-Lite parallel access, controlled by the
parameter C_DEBUG_INTERFACE.
See the MicroBlaze Debug Module (MDM) LogiCORE IP Product Guide (PG115) for a detailed description of the MDM features.
The basic debugging features enabled by setting C_DEBUG_ENABLED to 1
(Basic) include:
- Configurable number of hardware breakpoints and watchpoints and unlimited software breakpoints
- External processor control enables debug tools to stop, reset, and single step MicroBlaze
- Read from and write to: memory, general purpose registers, and special purpose register, except EAR, EDR, ESR, BTR, and PVR0 - PVR12, which can only be read
- Support for multiple processors
The extended debugging features enabled by setting C_DEBUG_ENABLED to 2
(Extended) include:
- Configurable number of performance monitoring event and latency counters
- Program Trace:
- Embedded program trace with configurable trace buffer size
- External program trace for multiple processors, provided by the MDM
- Non-intrusive profiling support with configurable profiling buffer size
- Cross trigger support between multiple processors, and external cross trigger inputs and outputs, provided by the MDM