The debug interface on MicroBlaze is designed to work with the MicroBlaze Debug Module (MDM) IP core. The MDM is controlled by the Xilinx System Debugger (XSDB) through the JTAG port of the FPGA. The MDM can control multiple MicroBlaze processors at the same time. The debug signals are grouped in the DEBUG bus.
The debug interface can be grouped in the DEBUG bus, using either JTAG serial signals (by setting C_DEBUG_INTERFACE = 0) or the AXI4-Lite compatible parallel signals (by setting C_DEBUG_INTERFACE = 1). The MDM configuration must also be set accordingly.
It is also possible to use only AXI4-Lite parallel signals (C_DEBUG_INTERFACE = 2) grouped in an AXI4 bus, in case the MDM is not used. However, this configuration is not supported by the tools.
The following table lists the debug signals on MicroBlaze.
| Signal Name | Description | VHDL Type | Kind |
|---|---|---|---|
| Dbg_Clk | JTAG clock from MDM | std_logic | serial in |
| Dbg_TDI | JTAG TDI from MDM | std_logic | serial in |
| Dbg_TDO | JTAG TDO to MDM | std_logic | serial out |
| Dbg_Reg_En | Debug register enable from MDM | std_logic_vector | serial in |
| Dbg_Shift 1 | JTAG BSCAN shift signal from MDM | std_logic | serial in |
| Dbg_Capture | JTAG BSCAN capture signal from MDM | std_logic | serial in |
| Dbg_Update | JTAG BSCAN update signal from MDM | std_logic | serial in |
| Debug_Rst 1 | Reset signal from MDM, active-High. Should be held for at least 1 Clk clock cycle. | std_logic | input |
| Dbg_Disable 2 | Debug disable signal from MDM | std_logic | input |
| Dbg_Trig_In 2 | Cross trigger event input to MDM | std_logic_vector | output |
| Dbg_Trig_Ack_In 2 | Cross trigger event input acknowledge from MDM | std_logic_vector | input |
| Dbg_Trig_Out 2 | Cross trigger action output from MDM | std_logic_vector | input |
| Dbg_Trig_Ack_Out 2 | Cross trigger action output acknowledge to MDM | std_logic_vector | output |
| Dbg_Trace_Data 3 | External Program Trace data output to MDM | std_logic_vector | output |
| Dbg_Trace_Valid 3 | External Program Trace valid to MDM | std_logic | output |
| Dbg_Trace_Ready 3 | External Program Trace ready from MDM | std_logic | input |
| Dbg_Trace_Clk 3 | External Program Trace clock from MDM | std_logic | input |
| Dbg_ARADDR 4 | Read address from MDM | std_logic_vector | parallel in |
| Dbg_ARREADY 4 | Read address ready to MDM | std_logic | parallel out |
| Dbg_ARVALID 4 | Read address valid from MDM | std_logic | parallel in |
| Dbg_AWADDR 4 | Write address from MDM | std_logic_vector | parallel in |
| Dbg_AWREADY 4 | Write address ready to MDM | std_logic | parallel out |
| Dbg_AWVALID 4 | Write address valid from MDM | std_logic | parallel in |
| Dbg_BREADY 4 | Write response ready to MDM | std_logic | parallel out |
| Dbg_BRESP 4 | Write response to MDM | std_logic_vector | parallel out |
| Dbg_BVALID 4 | Write response valid from MDM | std_logic | parallel in |
| Dbg_RDATA 4 | Read data to MDM | std_logic_vector | parallel out |
| Dbg_RREADY 4 | Read data ready to MDM | std_logic | parallel out |
| Dbg_RRESP 4 | Read data response to MDM | std_logic_vector | parallel out |
| Dbg_RVALID 4 | Read data valid from MDM | std_logic | parallel in |
| Dbg_WDATA 4 | Write data from MDM | std_logic_vector | parallel in |
| Dbg_WREADY 4 | Write data ready to MDM | std_logic | parallel out |
| Dbg_WVALID 4 | Write data valid from MDM | std_logic | parallel in |
| DEBUG_ACLK 4 | Debug clock, must be same as Clk | std_logic | parallel in |
| DEBUG_ARESET 4 | Debug reset, must be same as Reset | std_logic | parallel in |
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