MicroBlaze supports cache
coherency, as well as invalidation of caches and translation look-aside buffers, using
the AXI Coherency Extension (ACE) defined in
AMBA AXI and ACE Protocol Specification
(ARM IHI0022E) AXI and ACE Protocol
Specification (Arm IHI 0022E). The coherency support
is enabled when the parameter C_INTERCONNECT is set to 3 (ACE).
Using ACE ensures coherency between the caches of all MicroBlaze processors in the coherency domain. The peripheral ports
(AXI_IP, AXI_DP) and local memory (ILMB, DLMB) are
outside the coherency domain.
Coherency is not supported with write-back data cache, wide cache interfaces
(more than 32-bit data), instruction cache streams, instruction cache victims or when
area optimization is enabled. In addition both C_ICACHE_ALWAYS_USED and
C_DCACHE_ALWAYS_USED must be set to 1.