Branch Target Register - 2025.1 English - UG984

The Branch Target Register (BTR) only exists if the MicroBlaze processor is configured to use exceptions. The register stores the branch target address for all delay slot branch instructions executed while MSR[EIP] = 0. If an exception is caused by an instruction in a delay slot (that is, ESR[DS]=1), the exception handler should return execution to the address stored in BTR instead of the normal exception return address stored in R17. When read with the MFS instruction, the BTR is specified by setting Sa = 0x000B. The BTR register is illustrated in the following figure and the following table provides bit descriptions and reset values.

When 64-bit MicroBlaze is enabled (C_DATA_SIZE = 64), the Branch Target Register has up to 64 bits, according to the C_ADDR_SIZE parameter, otherwise it has 32 bits.