XPM_MEMORY_SPRAM - XPM_MEMORY_SPRAM - 2026.1 English - Parameterized Macro: Single Port RAM

Parameterized Macro: Single Port RAM

MACRO_GROUP: XPM
MACRO_SUBGROUP: XPM_MEMORY
Families: UltraScale, UltraScale+

Introduction

This macro instantiates Single Port RAM. Port A performs reads and writes to the memory.

The following describes the basic read and write port usage of an XPM_MEMORY instance.

All synchronous signals are sensitive to the rising edge of clka, assumed to be a buffered and toggling clock signal that behaves according to target device and memory primitive requirements.
A read operation is performed implicitly on address addra combinatorially. The data output registers on each clka cycle when ena is asserted.
Read data appears on the douta port READ_LATENCY_A clka cycles after the associated read operation.
A write operation is explicitly performed, writing dina to address addra, when both ena and wea are asserted on each clka cycle.
The value of ena gates all read and write operations on the initiating clka cycle, regardless of input or output latencies. The addra and wea inputs have no effect when ena is de-asserted on the coincident clka cycle.
The behavior of douta with respect to the combination of dina and addra is a function of WRITE_MODE_A.
When rsta is asserted on a clka cycle, the final output register resets immediately but synchronously to READ_RESET_VALUE_A, irrespective of READ_LATENCY_A.
When regcea is asserted and rsta is de-asserted on a clka cycle, the final output register captures and outputs the value from the previous pipeline register.
Undriven or unknown values provided on module inputs produce undefined memory array and output port behavior.
Using MEMORY INIT PARAM limits the maximum supported memory size to 4K bits.
Memory initialization with Asymmetric Byte Write Enable is not supported.
For better timing performance in larger memories (>1 Mb), use CASCADE_HEIGHT of 1 with sufficient read latencies.
Choosing the Invalid Configuration will result in a DRC error.

Note: Writing to an out-of-range address location may overwrite a valid address location when effective address bits match to a physical memory address location.

The use of UltraRAM’s dedicated input and output registers are controlled by synthesis based on the READ_LATENCY_B value. For example, if 4 UltraRAMs are in cascade and the READ_LATENCY_B is ≥ 4, then synthesis will absorb as much registers inside UltraRAM primitive as possible.
For UltraRAM's, OREG enabled when READ_LATENCY_B >= 3 in all write modes.
For larger memories (≥2 MB), use a read latency > 8 because the default cascade height used by Vivado synthesis is 8.

Timing Diagrams

Note: The UltraRAM primitive does not support write/read access in the clock cycle just before the rising edge that recognizes sleep assertion when its OREG attribute is set to TRUE. For UltraRAM configurations, do not perform write/read access in the clock cycle just before sleep assertion.

ECC Modes

Only the UltraRAM primitives support ECC when the memory type is set to Single Port RAM. The three ECC modes supported are:

Both encode and decode
Encode only
Decode only

The three ECC modes use the same read and write behavior described in the Introduction section above. Refer to the “Built-in Error Correction” section in the UltraScale Architecture Memory Resources User Guide (UG573) for details on this feature like Error Injection and syndrome bits calculations.

Each ECC mode restricts the WRITE_DATA_WIDTH_A, READ_DATA_WIDTH_A, and MEMORY_SIZE attributes.

Both encode and decode WRITE_DATA_WIDTH_A and READ_DATA_WIDTH_A must be multiples of 64-bits. Violating this rule will results in a DRC in XPM_Memory.
Encode only WRITE_DATA_WIDTH_A must be a multiple of 64 bits and READ_DATA_WIDTH_A must be a multiple of 72-bits. MEMORY_SIZE must be a multiple of READ_DATA_WIDTH_A. Violating these rules will result in a DRC.
Decode only WRITE_DATA_WIDTH_A must be a multiple of 72 bits and READ_DATA_WIDTH_A must be a multiple of 64-bits. MEMORY_SIZE must be a multiple of WRITE_DATA_WIDTH_A. Violating these rules will result in a DRC.

ECC does not support the following:

Asymmetry
Initialization
Reset (neither non-zero reset value nor reset assertion)

Note: ECC uses a hard-ECC block available in the BRAM/URAM macro and the data width needs to be a multiple of 64/72. Use ECC IP for other data width combinations.

Auto Sleep Mode

This feature applies only when MEMORY_PRIMITIVE is URAM, and UltraRAM controls it internally to check when it can enter sleep mode and when it needs to wake up. This provides power savings without explicitly controlling the SLEEP Pin.
AUTO_SLEEP_TIME = 0 disables the feature. When AUTO_SLEEP_TIME is non-zero, XPM_MEMORY constructs pipeline registers equal to AUTO_SLEEP_TIME on all input signals except rst[a|b].
If AUTO_SLEEP_TIME is too low, UltraRAM enters sleep and wakeup too often, which can cause higher power consumption.
The following formula calculates the number of sleep cycles achieved:
- If number of consecutive inactive cycles is <AUTO_SLEEP_TIME, then number of sleep cycles = 0.
- If number of consecutive inactive cycles is ≥AUTO_SLEEP_TIME, then number of consecutive sleep cycles = Number of consecutive inactive cycles – 3.
- An inactive cycle is a cycle with no Read/Write operation from either port.
The latency between the read operation and data arrival at dout[a|b] is AUTO_SLEEP_TIME + READ_LATENCY_[A|B] clock cycles (assuming REGCE is high when the output data pipeline exists).
When READ_LATENCY_[A|B] is 1 or 2, XPM_Memory behaviorally models the AUTO SLEEP feature and forces ‘x’ on DOUT[A|B] when the RAM is in Auto Sleep Mode. When READ_LATENCY_[A|B] is greater than 2, ‘x’ does not propagate to DOUT[A|B] because the output registers get the clock enable (delayed read enable) after UltraRAM comes out of sleep mode.
The Auto Sleep mode is most effective for larger memory sizes or for memory with very little activity.

The following timing diagrams show Auto Sleep Mode at various read latencies.

Port Descriptions

Port	Direction	Width	Domain	Sense	Handling if Unused	Function
addra	Input	ADDR_WIDTH_A	clka	NA	Active	Address for port A write and read operations.
clka	Input	1	NA	EDGE_RISING	Active	Clock signal for port A.
dbiterra	Output	1	clka	LEVEL_HIGH	DoNotCare	Status signal to indicate double bit error occurrence on the data output of port A.
dina	Input	WRITE_DATA_WIDTH_A	clka	NA	Active	Data input for port A write operations.
douta	Output	READ_DATA_WIDTH_A	clka	NA	Active	Data output for port A read operations.
ena	Input	1	clka	LEVEL_HIGH	Active	Memory enable signal for port A. Must be high on clock cycles when you initiate read or write operations. Pipelined internally.
injectdbiterra	Input	1	clka	LEVEL_HIGH	0	Controls double bit error injection on input data when ECC enabled (Error injection capability is not available in "decode_only" mode).
injectsbiterra	Input	1	clka	LEVEL_HIGH	0	Controls single bit error injection on input data when ECC enabled (Error injection capability is not available in "decode_only" mode).
regcea	Input	1	clka	LEVEL_HIGH	1	Clock Enable for the last register stage on the output data path.
rsta	Input	1	clka	LEVEL_HIGH	Active	Reset signal for the final port A output register stage. Synchronously resets output port douta to the value specified by parameter READ_RESET_VALUE_A.
sbiterra	Output	1	clka	LEVEL_HIGH	DoNotCare	Status signal to indicate single bit error occurrence on the data output of port A.
sleep	Input	1	NA	LEVEL_HIGH	0	sleep signal to enable the dynamic power saving feature.
wea	Input	WRITE_DATA_WIDTH_A / BYTE_WRITE_WIDTH_A	clka	LEVEL_HIGH	Active	Write enable vector for port A input data port dina. 1 bit wide for word-wide writes. In byte-wide write configurations, each bit controls the writing one byte of dina to address addra. For example, to synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A is 32, wea is 4'b0010.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
ADDR_WIDTH_A	DECIMAL	1 to 20	6	Specify the width of the port A address port addra, in bits. Must be large enough to access the entire memory from port A, that is, >= $clog2(MEMORY_SIZE/[WRITE\|READ]_DATA_WIDTH_A).
AUTO_SLEEP_TIME	DECIMAL	0 to 15	0	Specify the number of clka cycles to auto sleep, if feature is available in architecture. 0: Disable auto sleep feature 3-15: Number of auto sleep latency cycles Do not change from the value provided in the template instantiation.
BYTE_WRITE_WIDTH_A	DECIMAL	1 to 4608	32	To enable byte-wide writes on port A, specify the byte width, in bits. 8: 8-bit byte-wide writes, legal when WRITE_DATA_WIDTH_A is an integer multiple of 8 9: 9-bit byte-wide writes, legal when WRITE_DATA_WIDTH_A is an integer multiple of 9 Or to enable word-wide writes on port A, specify the same value as for WRITE_DATA_WIDTH_A.
CASCADE_HEIGHT	DECIMAL	0 to 64	0	0: No Cascade Height: Enables Vivado Synthesis to choose. 1 or more: Vivado Synthesis sets the specified value as Cascade Height.
ECC_BIT_RANGE	STRING	String	"7:0"	This parameter is only used by synthesis. Specify the ECC bit range on the provided data. "7:0": it specifies lower 8 bits are ECC bits.
ECC_MODE	STRING	"no_ecc", "both_encode_and_decode", "decode_only", "encode_only"	"no_ecc"	"no_ecc": Disables ECC "encode_only": Enables ECC Encoder only "decode_only": Enables ECC Decoder only "both_encode_and_decode": Enables both ECC Encoder and Decoder
ECC_TYPE	STRING	"none", "ECCHSIAO32-7", "ECCHSIAO64-8", "ECCHSIAO128-9", "ECCH32-7", "ECCH64-8"	"none"	This parameter is only used by synthesis. Specify the algorithm used to generate the ecc bits outside the XPM Memory. XPM Memory does not perform ECC operation with this parameter. When ECC_MODE is not equal to no_ecc, the macro ignores the ECC_TYPE parameter and sets its value to none. "none": No ECC "ECCH32-7": Uses 32 bit ECC Hamming algorithm "ECCH64-8": Uses 64 bit ECC Hamming algorithm "ECCHSIAO32-7": Uses 32 bit ECC HSIAO algorithm "ECCHSIAO64-8": Uses 64 bit ECC HSIAO algorithm "ECCHSIAO128-9": Uses 128 bit ECC HSIAO algorithm
IGNORE_INIT_SYNTH	DECIMAL	0 to 1	0	0: If specified, the initialization file applies to both simulation and synthesis. 1: If specified, the initialization file applies to only simulation and ignores synthesis.
MEMORY_INIT_FILE	STRING	String	"none"	Specify "none" (including quotes) for no memory initialization, or specify the name of a memory initialization file. Enter only the name of the file with .mem extension, including quotes but without path (for example, "my_file.mem"). File format must be ASCII and consist of only hexadecimal values organized into the specified depth by narrowest data width generic value of the memory. Initialization of memory happens through the file name specified only when parameter MEMORY_INIT_PARAM value is equal to "". When using XPM_MEMORY in a project, add the specified file to the Vivado project as a design source.
MEMORY_INIT_PARAM	STRING	String	"0"	Specify "" or "0" (including quotes) for no memory initialization through parameter, or specify the string containing the hex characters. Enter only hex characters with each location separated by delimiter (,). Parameter format must be ASCII and consist of only hexadecimal values organized into the specified depth by narrowest data width generic value of the memory. For example, if the narrowest data width is 8, and the depth of memory is 8 locations, then pass the parameter value as follows. parameter MEMORY_INIT_PARAM = "AB,CD,EF,1,2,34,56,78" Where "AB" is the 0th location and "78" is the 7th location.
MEMORY_OPTIMIZATION	STRING	"true", "false"	"true"	Specify "true" to enable the optimization of unused memory or bits in the memory structure. Specify "false" to disable the optimization of unused memory or bits in the memory structure
MEMORY_PRIMITIVE	STRING	"auto", "block", "distributed", "mixed", "ultra"	"auto"	Specifies the memory primitive (resource type) to use. "auto": Enables Vivado Synthesis to choose "distributed": Distributed memory "block": Block memory "ultra": UltraRAM memory "mixed": Mixed memory NOTE: Selecting Block RAM or UltraRAM specific features, like ECC or Asymmetry, with MEMORY_PRIMITIVE set to "auto" might cause a behavior mismatch.
MEMORY_SIZE	DECIMAL	2 to 150994944	2048	Specify the total memory array size, in bits. For example, enter 65536 for a 2kx32 RAM. When you enable ECC and set it to "encode_only", then the memory size has to be multiples of READ_DATA_WIDTH_A When you enable ECC and set it to "decode_only", then the memory size has to be multiples of WRITE_DATA_WIDTH_A
MESSAGE_CONTROL	DECIMAL	0 to 1	0	Specify 1 to enable the dynamic message reporting such as collision warnings, and 0 to disable the message reporting
RAM_DECOMP	STRING	"auto", "area", "power"	"auto"	Specifies the decomposition of the memory. "auto": Synthesis selects default. "power": Synthesis selects a strategy to reduce switching activity of RAMs and maps using widest configuration possible. "area": Synthesis selects a strategy to reduce RAM resource count.
READ_DATA_WIDTH_A	DECIMAL	1 to 4608	32	Specify the width of the port A read data output port douta, in bits. The values of READ_DATA_WIDTH_A and WRITE_DATA_WIDTH_A must be equal. When you enable ECC and set it to "encode_only", then READ_DATA_WIDTH_A has to be multiples of 72-bits. When you enable ECC and set it to "decode_only" or "both_encode_and_decode", then READ_DATA_WIDTH_A has to be multiples of 64-bits.
READ_LATENCY_A	DECIMAL	0 to 100	2	Specify the number of register stages in the port A read data pipeline. Read data output to port douta takes this number of clka cycles. Targeting block memory requires a value of 1 or larger. 1 causes use of memory latch only; 2 causes use of output register. Targeting distributed memory requires a value of 0 or larger. 0 indicates combinatorial output. Values larger than 2 synthesize additional flip-flops that are not retimed into memory primitives.
READ_RESET_VALUE_A	STRING	String	"0"	Specify the reset value of the port A final output register stage in response to rsta input port assertion. Because this parameter is a string, you must specify the hex values inside double quotes. For example, If the read data width is 8, then specify READ_RESET_VALUE_A = "EA"; When you enable ECC, then reset value is not supported.
RST_MODE_A	STRING	"SYNC", "ASYNC"	"SYNC"	Describes the behavior of the reset "SYNC": when you apply reset, it synchronously resets output port douta to the value specified by parameter READ_RESET_VALUE_A "ASYNC": when you apply reset, it asynchronously resets output port douta to zero
SIM_ASSERT_CHK	DECIMAL	0 to 1	0	0: Disable simulation message reporting. This does not report messages related to potential misuse. 1: Enable simulation message reporting. This reports messages related to potential misuse.
USE_MEM_INIT	DECIMAL	0 to 1	1	Specify 1 to enable the generation of the following message and 0 to disable generation of the following message completely. "INFO - MEMORY_INIT_FILE and MEMORY_INIT_PARAM together specifies no memory initialization. Initial memory contents will be all 0s." NOTE: The tool generates this message only when there is no Memory Initialization specified either through file or Parameter.
USE_MEM_INIT_MMI	DECIMAL	0 to 1	0	Specify 1 to expose this memory information for writing to the MMI file.
WAKEUP_TIME	STRING	"disable_sleep", "use_sleep_pin"	"disable_sleep"	Specify "disable_sleep" to disable dynamic power saving option, and specify "use_sleep_pin" to enable the dynamic power saving option
WRITE_DATA_WIDTH_A	DECIMAL	1 to 4608	32	Specify the width of the port A write data input port dina, in bits. The values of WRITE_DATA_WIDTH_A and READ_DATA_WIDTH_A must be equal. When you enable ECC and set it to "encode_only" or "both_encode_and_decode", then WRITE_DATA_WIDTH_A must be multiples of 64-bits. When you enable ECC and set it to "decode_only", then WRITE_DATA_WIDTH_A must be multiples of 72-bits.
WRITE_MODE_A	STRING	"read_first", "no_change", "write_first"	"read_first"	Write mode behavior for port A output data port, douta.
WRITE_PROTECT	DECIMAL	0 to 1	1	This setting defaults to 1. This setting requires enable and write enable to protect write operations and places the LUT before the memory. This configuration provides the default memory access behavior. When 0, this setting disables write protection and connects write enable (WE) directly to memory. NOTE: Disable this option only if advanced users can guarantee they never assert write enable (WE) without enable (EN).

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library xpm;
use xpm.vcomponents.all;


-- xpm_memory_spram: Single Port RAM
-- Xilinx Parameterized Macro, version 2026.1

xpm_memory_spram_inst : xpm_memory_spram
generic map (
   ADDR_WIDTH_A => 6,              -- DECIMAL
   AUTO_SLEEP_TIME => 0,           -- DECIMAL
   BYTE_WRITE_WIDTH_A => 32,       -- DECIMAL
   CASCADE_HEIGHT => 0,            -- DECIMAL
   ECC_BIT_RANGE => "7:0",         -- String
   ECC_MODE => "no_ecc",           -- String
   ECC_TYPE => "none",             -- String
   IGNORE_INIT_SYNTH => 0,         -- DECIMAL
   MEMORY_INIT_FILE => "none",     -- String
   MEMORY_INIT_PARAM => "0",       -- String
   MEMORY_OPTIMIZATION => "true",  -- String
   MEMORY_PRIMITIVE => "auto",     -- String
   MEMORY_SIZE => 2048,            -- DECIMAL
   MESSAGE_CONTROL => 0,           -- DECIMAL
   RAM_DECOMP => "auto",           -- String
   READ_DATA_WIDTH_A => 32,        -- DECIMAL
   READ_LATENCY_A => 2,            -- DECIMAL
   READ_RESET_VALUE_A => "0",      -- String
   RST_MODE_A => "SYNC",           -- String
   SIM_ASSERT_CHK => 0,            -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
   USE_MEM_INIT => 1,              -- DECIMAL
   USE_MEM_INIT_MMI => 0,          -- DECIMAL
   WAKEUP_TIME => "disable_sleep", -- String
   WRITE_DATA_WIDTH_A => 32,       -- DECIMAL
   WRITE_MODE_A => "read_first",   -- String
   WRITE_PROTECT => 1              -- DECIMAL
)
port map (
   sleep => sleep, -- 1-bit input: sleep signal to enable the dynamic power saving feature.
   clka => clka, -- 1-bit input: Clock signal for port A.
   rsta => rsta, -- 1-bit input: Reset signal for the final port A output register stage. Synchronously resets output port
                                     -- douta to the value specified by parameter READ_RESET_VALUE_A.

   ena => ena, -- 1-bit input: Memory enable signal for port A. Must be high on clock cycles when you initiate read or write
                                     -- operations. Pipelined internally.

   regcea => regcea, -- 1-bit input: Clock Enable for the last register stage on the output data path.
   wea => wea, -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector for port A input data port dina. 1
                                     -- bit wide for word-wide writes. In byte-wide write configurations, each bit controls the writing one byte
                                     -- of dina to address addra. For example, to synchronously write only bits [15-8] of dina when
                                     -- WRITE_DATA_WIDTH_A is 32, wea is 4'b0010.

   addra => addra, -- ADDR_WIDTH_A-bit input: Address for port A write and read operations.
   dina => dina, -- WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
   injectsbiterra => injectsbiterra, -- 1-bit input: Controls single bit error injection on input data when ECC enabled (Error injection
                                     -- capability is not available in "decode_only" mode).

   injectdbiterra => injectdbiterra, -- 1-bit input: Controls double bit error injection on input data when ECC enabled (Error injection
                                     -- capability is not available in "decode_only" mode).

   douta => douta, -- READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
   sbiterra => sbiterra, -- 1-bit output: Status signal to indicate single bit error occurrence on the data output of port A.
   dbiterra => dbiterra -- 1-bit output: Status signal to indicate double bit error occurrence on the data output of port A.
);

-- End of xpm_memory_spram_inst instantiation

Verilog Instantiation Template


// xpm_memory_spram: Single Port RAM
// Xilinx Parameterized Macro, version 2026.1

xpm_memory_spram #(
   .ADDR_WIDTH_A(6),              // DECIMAL
   .AUTO_SLEEP_TIME(0),           // DECIMAL
   .BYTE_WRITE_WIDTH_A(32),       // DECIMAL
   .CASCADE_HEIGHT(0),            // DECIMAL
   .ECC_BIT_RANGE("7:0"),         // String
   .ECC_MODE("no_ecc"),           // String
   .ECC_TYPE("none"),             // String
   .IGNORE_INIT_SYNTH(0),         // DECIMAL
   .MEMORY_INIT_FILE("none"),     // String
   .MEMORY_INIT_PARAM("0"),       // String
   .MEMORY_OPTIMIZATION("true"),  // String
   .MEMORY_PRIMITIVE("auto"),     // String
   .MEMORY_SIZE(2048),            // DECIMAL
   .MESSAGE_CONTROL(0),           // DECIMAL
   .RAM_DECOMP("auto"),           // String
   .READ_DATA_WIDTH_A(32),        // DECIMAL
   .READ_LATENCY_A(2),            // DECIMAL
   .READ_RESET_VALUE_A("0"),      // String
   .RST_MODE_A("SYNC"),           // String
   .SIM_ASSERT_CHK(0),            // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
   .USE_MEM_INIT(1),              // DECIMAL
   .USE_MEM_INIT_MMI(0),          // DECIMAL
   .WAKEUP_TIME("disable_sleep"), // String
   .WRITE_DATA_WIDTH_A(32),       // DECIMAL
   .WRITE_MODE_A("read_first"),   // String
   .WRITE_PROTECT(1)              // DECIMAL
)
xpm_memory_spram_inst (
   .sleep(sleep), // 1-bit input: sleep signal to enable the dynamic power saving feature.
   .clka(clka), // 1-bit input: Clock signal for port A.
   .rsta(rsta), // 1-bit input: Reset signal for the final port A output register stage. Synchronously resets output port
                                    // douta to the value specified by parameter READ_RESET_VALUE_A.

   .ena(ena), // 1-bit input: Memory enable signal for port A. Must be high on clock cycles when you initiate read or write
                                    // operations. Pipelined internally.

   .regcea(regcea), // 1-bit input: Clock Enable for the last register stage on the output data path.
   .wea(wea), // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector for port A input data port dina. 1 bit
                                    // wide for word-wide writes. In byte-wide write configurations, each bit controls the writing one byte of
                                    // dina to address addra. For example, to synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
                                    // is 32, wea is 4'b0010.

   .addra(addra), // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
   .dina(dina), // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
   .injectsbiterra(injectsbiterra), // 1-bit input: Controls single bit error injection on input data when ECC enabled (Error injection capability
                                    // is not available in "decode_only" mode).

   .injectdbiterra(injectdbiterra), // 1-bit input: Controls double bit error injection on input data when ECC enabled (Error injection capability
                                    // is not available in "decode_only" mode).

   .douta(douta), // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
   .sbiterra(sbiterra), // 1-bit output: Status signal to indicate single bit error occurrence on the data output of port A.
   .dbiterra(dbiterra) // 1-bit output: Status signal to indicate double bit error occurrence on the data output of port A.
);

// End of xpm_memory_spram_inst instantiation

XPM_MEMORY_SPRAM - XPM_MEMORY_SPRAM - 2026.1 English - Parameterized Macro: Single Port RAM - UG974

UltraScale Architecture Libraries Guide (UG974)