Primitive: 32-Deep by 1-Wide Static Synchronous RAM
- PRIMITIVE_GROUP: CLB
- PRIMITIVE_SUBGROUP: LUTRAM
- Families: UltraScale, UltraScale+
Introduction
This design element is a 32-bit deep by 1-bit wide static random access memory with synchronous write capability. When the write enable is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When (WE) is High, any positive transition on (WCLK) loads the data on the data input (D) into the memory cell selected by the 5-bit address (A4-A0). For predictable performance, address and data inputs must be stable before a Low-to-High (WCLK) transition. This RAM block assumes an active-High (WCLK). However, (WCLK) can be active-High or active-Low. Any inverter placed on the (WCLK) input net is absorbed into the block.
The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by the values on the address pins.
You can use the INIT attribute to specify the initial contents of the RAM. If left unspecified, the initial contents default to all zeros.
Logic Table
| Inputs | Outputs | ||
|---|---|---|---|
| WE (Mode) | WCLK | D | O |
| 0 (read) | X | X | Data |
| 1 (read) | 0 | X | Data |
| 1 (read) | 1 | X | Data |
| 1 (write) | ↑ | D | D |
| 1 (read) | ↓ | X | Data |
Design Entry Method
| Instantiation | Yes |
| Inference | Recommended |
| IP Catalog | No |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| INIT | HEX | Any 32-bit value | All zeros | Specifies the initial contents of the RAM. |
| IS_WCLK_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the WCLK pin. |