RAM32X16DR8 - 2025.1 English - Primitive: Asymmetric LUTRAM

Primitive: Asymmetric LUTRAM

PRIMITIVE_GROUP: CLB
PRIMITIVE_SUBGROUP: LUTRAM
Families: UltraScale, UltraScale+

Introduction

This design element is a 32-Deep Asymmetric LUTRAM. The write size (32*14) is twice the read size (64*7) and fits into a single slice.

Port Descriptions

Port	Direction	Width	Function
ADDRA<5:0>	Input	6	Read port A address input.
ADDRB<5:0>	Input	6	Read port B address input.
ADDRC<5:0>	Input	6	Read port C address input.
ADDRD<5:0>	Input	6	Read port D address input.
ADDRE<5:0>	Input	6	Read port E address input.
ADDRF<5:0>	Input	6	Read port F address input.
ADDRG<5:0>	Input	6	Read port G address input.
ADDRH<4:0>	Input	5	Read/write port H address input.
DIA<1:0>	Input	2	RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRA.
DIB<1:0>	Input	2	RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRB.
DIC<1:0>	Input	2	RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRC.
DID<1:0>	Input	2	RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRD.
DIE<1:0>	Input	2	RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRE.
DIF<1:0>	Input	2	RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRF.
DIG<1:0>	Input	2	RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRG.
DIH<1:0>	Input	2	RAM 2-bit data write input addressed by ADDRH, read addressed by ADDRH.
DOA	Output	1	Read port data outputs addressed by ADDRA.
DOB	Output	1	Read port data outputs addressed by ADDRB.
DOC	Output	1	Read port data outputs addressed by ADDRC.
DOD	Output	1	Read port data outputs addressed by ADDRD.
DOE	Output	1	Read port data outputs addressed by ADDRE.
DOF	Output	1	Read port data outputs addressed by ADDRF.
DOG	Output	1	Read port data outputs addressed by ADDRG.
DOH<1:0>	Output	2	Read port data outputs addressed by ADDRH.
WCLK	Input	1	Write clock.
WE	Input	1	Write Enable.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
IS_WCLK_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether or not to use the optional inversion on the WCLK pin.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- RAM32X16DR8: Asymmetric LUTRAM
--              UltraScale
-- Xilinx HDL Language Template, version 2025.1

RAM32X16DR8_inst : RAM32X16DR8
port map (

);

-- End of RAM32X16DR8_inst instantiation

Verilog Instantiation Template


// RAM32X16DR8: Asymmetric LUTRAM
//              UltraScale
// Xilinx HDL Language Template, version 2025.1

RAM32X16DR8 RAM32X16DR8_inst (

);

// End of RAM32X16DR8_inst instantiation