PULLUP - 2025.1 English - Primitive: I/O Pullup - UG974

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2025-05-29
Version
2025.1 English

Primitive: I/O Pullup

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: WEAK_DRIVER
  • Families: UltraScale, UltraScale+

Introduction

The design element is a weak pullup element that pulls an undriven I/O to a logic one state. For example, if the I/O is 3-stated and not driven by any other element, a logic 1 will exist on the I/O.

Port Descriptions

Port Direction Width Function
O Output 1 Pullup output. Connect directly to a top-level port in the design.

Design Entry Method

Instantiation Yes
Inference Yes, via property
IP and IP Integrator Catalog No

VHDL Instantiation Template

Verilog Instantiation Template

Related Information