Primitive: Base Phase-Locked Loop (PLL)
- PRIMITIVE_GROUP: CLOCK
- PRIMITIVE_SUBGROUP: PLL
- Families: UltraScale+
Introduction
The PLLE4 is used for high-speed I/O clocking using Bitslice components as well as general clocking requirements. In general, the PLLE4 has less jitter and reduced power characteristics compared to the MMCME4 which makes it preferable for clocking behaviors that do not require features only available to the MMCME4.
Design Entry Method
| Instantiation | No |
| Inference | No |
| IP and IP Integrator Catalog | Yes |