PLLE4_ADV - PLLE4_ADV - 2026.1 English - Primitive: Advanced Phase-Locked Loop (PLL) - UG974

UltraScale Architecture Libraries Guide (UG974)
Document ID
UG974
Release Date
2026-06-23
Version
2026.1 English

Primitive: Advanced Phase-Locked Loop (PLL)

  • PRIMITIVE_GROUP: CLOCK
  • PRIMITIVE_SUBGROUP: PLL
Page-1 Sheet.1 PLLE4_ADV PLLE4_ADV Text Line.88 CLKOUT1B CLKOUT1B Text Line.93 CLKOUT1 CLKOUT1 Text Line.32 DCLK DCLK Text Line.33 DEN DEN Text Line.34 DI[15:0] DI[15:0] Text Line.35 DO[15:0] DO[15:0] Text Line.36 DRDY DRDY Text Line.37 DWE DWE Text Line.38 LOCKED LOCKED Text Line.39 PWRDWN PWRDWN Sheet.12 RST RST Text Line.5 DADDR[6:0] DADDR[6:0] Text Line.6 CLKOUTPHYEN CLKOUTPHYEN Text Line.7 CLKIN CLKIN Text Line.8 CLKFBIN CLKFBIN Text Line.9 CLKOUT0 CLKOUT0 Text Line.10 CLKOUTPHY CLKOUTPHY Text Line.12 CLKFBOUT CLKFBOUT Text Line.11 CLKOUT0B CLKOUT0B D Flip-Flop.12 D Flip-Flop.42 Sheet.23 X15110-102615 Sheet.24 Sheet.25 Sheet.26 X15110-061319

Introduction

The PLLE4 is used for high-speed I/O clocking using Bitslice components as well as general clocking requirements. In general, the PLLE4 has less jitter and reduced power characteristics compared to the MMCME4 which makes it preferable for clocking behaviors that do not require features only available to the MMCME4.

Port Descriptions

Port Direction Width Function
CLKFBIN Input 1 Feedback clock pin to the PLL
CLKFBOUT Output 1 Dedicated PLL Feedback clock output
CLKIN Input 1 Input clock
CLKOUTPHY Output 1 General clock output connected to I/O Bitslice components
CLKOUTPHYEN Input 1 Enable signal for CLKOUTPHY
CLKOUT0 Output 1 General clock output CLKOUT0. Generally connected to a global buffer
CLKOUT0B Output 1 Inverted CLKOUT0
CLKOUT1 Output 1 General clock output CLKOUT1
CLKOUT1B Output 1 Inverted CLKOUT1
DADDR<6:0> Input 7 The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeroes
DCLK Input 1 The DCLK signal is the reference clock for the dynamic reconfiguration port
DEN Input 1 The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low
DI<15:0> Input 16 The dynamic reconfiguration output bus provides PLL data output when using dynamic reconfiguration
DO<15:0> Output 16 The dynamic reconfiguration output bus provides PLL data output when using dynamic reconfiguration
DRDY Output 1 The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the PLLs dynamic reconfiguration feature
DWE Input 1 The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, it must be tied Low
LOCKED Output 1 An output from the PLL that indicates when the PLL has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The PLL automatically locks after power on, no extra reset is required. LOCKED will be deasserted if the input clock stops or the phase alignment is violated (e.g., input clock phase shift). The PLL must be reset after LOCKED is deasserted.
PWRDWN Input 1 Powers down instantiated but unused PLLs
RST Input 1 The RST signal is an asynchronous reset for the PLL. The PLL will synchronously re-enable itself when this signal is released and go through a new phase alignment and lock cycle. A reset is required when the input clock conditions change (e.g., frequency)

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog Recommended

Available Attributes

Attribute Type Allowed Values Default Description
CLKFBOUT_MULT DECIMAL 2 to 21 5 Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, will determine the output frequency
CLKFBOUT_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the PLL
CLKIN_PERIOD FLOAT(nS) 0.000 to 14.286 0.000 Specifies the input period in ns to the PLL CLKIN input. Resolution is down to the ps (3 decimal places). For example a value of 33.333 would indicate a 30 MHz input clock. This information is mandatory and must be supplied
CLKOUTPHY_MODE STRING "VCO_2X", "VCO", "VCO_HALF" "VCO_2X" Specifies the frequency of the CLKOUTPHY clock output
CLKOUT0_DIVIDE DECIMAL 1 to 128 1 Specifies the amount to divide the CLKOUT0 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency
CLKOUT0_DUTY _CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT0 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle)
CLKOUT0_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT0 output
CLKOUT1_DIVIDE DECIMAL 1 to 128 1 Specifies the amount to divide the CLKOUT1 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency
CLKOUT1_DUTY _CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT1 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle)
CLKOUT1_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT1 output
COMPENSATION STRING "AUTO", "BUF_IN", "INTERNAL", "PHY _ALIGN" "AUTO" Clock input compensation. In general, should be set to AUTO. Defines how the PLL feedback compensation is configured.
  • "AUTO" - Tools automatically determine proper compensation settings based on how the PLL feedback path is connected.
  • "INTERNAL" - Indicates the PLL is using its own internal feedback path so no delay is being compensated.
  • "BUF_IN" - Indicates that the configuration does not match with the other compensation modes and no delay will be compensated. This is the case if a clock input is driven by a BUFG for instance.
DIVCLK_DIVIDE DECIMAL 1 to 15 1 Specifies the division ratio for all output clocks with respect to the input clock. Effectively divides the CLKIN going into the PFD
IS_CLKFBIN _INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKFBIN pin of this component
IS_CLKIN _INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKIN pin of this component
IS_PWRDWN _INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the PWRDWN pin of this component
IS_RST_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the RST pin of this component
REF_JITTER 3 significant digit FLOAT 0.000 to 0.999 0.010 Allows specification of the expected jitter on CLKIN in order to better optimize PLL performance. A bandwidth setting of OPTIMIZED will attempt to choose the best parameter for input clocking when unknown. If known, then the value provided should be specified in terms of the UI percentage (the maximum peak to peak value) of the expected jitter on the input clock
STARTUP_WAIT STRING "FALSE", "TRUE" "FALSE" Delays configuration DONE signal from asserting until PLL is locked

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration. 
Library UNISIM;
use UNISIM.vcomponents.all;

-- PLLE4_ADV: Advanced Phase-Locked Loop (PLL)
--            UltraScale
-- Xilinx HDL Language Template, version 2026.1

PLLE4_ADV_inst : PLLE4_ADV
generic map (
   CLKFBOUT_MULT => 5,         -- Multiply value for all CLKOUT
   CLKFBOUT_PHASE => 0.0,      -- Phase offset in degrees of CLKFB
   CLKIN_PERIOD => 0.0,        -- Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
   CLKOUT0_DIVIDE => 1,        -- Divide amount for CLKOUT0
   CLKOUT0_DUTY_CYCLE => 0.5,  -- Duty cycle for CLKOUT0
   CLKOUT0_PHASE => 0.0,       -- Phase offset for CLKOUT0
   CLKOUT1_DIVIDE => 1,        -- Divide amount for CLKOUT1
   CLKOUT1_DUTY_CYCLE => 0.5,  -- Duty cycle for CLKOUT1
   CLKOUT1_PHASE => 0.0,       -- Phase offset for CLKOUT1
   CLKOUTPHY_MODE => "VCO_2X", -- Frequency of the CLKOUTPHY
   COMPENSATION => "AUTO",     -- Clock input compensation
   DIVCLK_DIVIDE => 1,         -- Master division value
   IS_CLKFBIN_INVERTED => '0', -- Optional inversion for CLKFBIN
   IS_CLKIN_INVERTED => '0',   -- Optional inversion for CLKIN
   IS_PWRDWN_INVERTED => '0',  -- Optional inversion for PWRDWN
   IS_RST_INVERTED => '0',     -- Optional inversion for RST
   REF_JITTER => 0.0,          -- Reference input jitter in UI
   STARTUP_WAIT => "FALSE"     -- Delays DONE until PLL is locked
)
port map (
   CLKFBOUT => CLKFBOUT,       -- 1-bit output: Feedback clock
   CLKOUT0 => CLKOUT0,         -- 1-bit output: General Clock output
   CLKOUT0B => CLKOUT0B,       -- 1-bit output: Inverted CLKOUT0
   CLKOUT1 => CLKOUT1,         -- 1-bit output: General Clock output
   CLKOUT1B => CLKOUT1B,       -- 1-bit output: Inverted CLKOUT1
   CLKOUTPHY => CLKOUTPHY,     -- 1-bit output: Bitslice clock
   DO => DO,                   -- 16-bit output: DRP data output
   DRDY => DRDY,               -- 1-bit output: DRP ready
   LOCKED => LOCKED,           -- 1-bit output: LOCK
   CLKFBIN => CLKFBIN,         -- 1-bit input: Feedback clock
   CLKIN => CLKIN,             -- 1-bit input: Input clock
   CLKOUTPHYEN => CLKOUTPHYEN, -- 1-bit input: CLKOUTPHY enable
   DADDR => DADDR,             -- 7-bit input: DRP address
   DCLK => DCLK,               -- 1-bit input: DRP clock
   DEN => DEN,                 -- 1-bit input: DRP enable
   DI => DI,                   -- 16-bit input: DRP data input
   DWE => DWE,                 -- 1-bit input: DRP write enable
   PWRDWN => PWRDWN,           -- 1-bit input: Power-down
   RST => RST                  -- 1-bit input: Reset
);

-- End of PLLE4_ADV_inst instantiation