Primitive: CLB MUX to connect two LUT6's Together
- PRIMITIVE_GROUP: CLB
- PRIMITIVE_SUBGROUP: MUXF
- Families: UltraScale, UltraScale+
Introduction
This design element is a two input multiplexer which, in combination with two LUT6 elements
will let you create any 7-input logic function, an 8-to-1 multiplexer, or other logic functions up to
13-bits wide all within a single CLB. Outputs of the LUT6 elements are connected to the I0 and I1 inputs of the
MUXF7. The S input is driven from any net. When Low, S selects I0. When High, S
selects I1.
Logic Table
| Inputs |
Outputs |
| S |
I0 |
I1 |
O |
| 0 |
I0 |
X |
I0 |
| 1 |
X |
I1 |
I1 |
| X |
0 |
0 |
0 |
| X |
1 |
1 |
1 |
Port Descriptions
| Port |
Direction |
Width |
Function |
| I0 |
Input |
1 |
MUX data input. Connects to the output of a LUT6 located in the same CLB. |
| I1 |
Input |
1 |
MUX data input. Connects to the output of a LUT6 located in the same CLB. |
| O |
Output |
1 |
Data output from the CLB MUX. |
| S |
Input |
1 |
Selects between the I0 (S=0) or I1 (S=1) inputs to the MUX. |
Design Entry Method
| Instantiation |
Yes |
| Inference |
Recommended |
| IP and IP Integrator Catalog |
No |
VHDL Instantiation Template
Verilog Instantiation Template