Primitive: Transparent Latch with Clock Enable and Asynchronous Preset
- PRIMITIVE_GROUP: REGISTER
- PRIMITIVE_SUBGROUP: LATCH
- Families: UltraScale, UltraScale+
Introduction
This design element is a transparent data latch with asynchronous preset and gate enable. When
the asynchronous preset input (PRE) is active, it overrides the other inputs and presets the data
(Q) output High. Q reflects the data (D) input while the gate (G) input and gate enable (GE)
are active and PRE is not active. If (GE) is Low, data on (D) cannot be latched. The data on the (D)
input during the gate transition is stored in the latch. The data on the (Q) output
remains unchanged as long as (G) or (GE) remains Low.
This latch is asynchronously initialized when power is applied.
When global set/reset (GSR) is active upon power-up or when GSR is
asserted via the STARTUP block,
the value of the INIT attribute is placed on the latch's output.
Logic Table
| Inputs |
Outputs |
| PRE |
GE |
G |
D |
Q |
| 1 |
X |
X |
X |
1 |
| 0 |
0 |
X |
X |
No Change |
| 0 |
1 |
1 |
D |
D |
| 0 |
1 |
0 |
X |
No Change |
| 0 |
1 |
↓ |
D |
D |
Port Descriptions
| Port |
Direction |
Width |
Function |
| D |
Input |
1 |
Data input |
| G |
Input |
1 |
Gate input. Polarity is determined by the IS_G_INVERTED attribute. |
| GE |
Input |
1 |
Active-High latch gate enable. |
| PRE |
Input |
1 |
Asynchronous preset. Polarity is determined by the IS_PRE_INVERTED attribute. |
| Q |
Output |
1 |
Data output |
Design Entry Method
| Instantiation |
Yes |
| Inference |
Yes |
| IP and IP Integrator Catalog |
No |
Available Attributes
| Attribute |
Type |
Allowed Values |
Default |
Description |
| INIT |
BINARY |
1'b1, 1'b0 |
1'b1 |
Sets the initial value of Q output after configuration or when GSR is asserted. |
|
Programmable Inversion Attributes: Specifies whether or not to use the optional inversion on specific pins of this component to change the
active polarity of the pin function. When set to 1 on a gate pin (G), it creates an active-Low latch.
When set to 1 on other pins, it changes the function to behave active-Low rather than active-High.
If an external inverter is specified on one of these associated pins, the Vivado Design Suite will automatically
set this attribute during the opt_design stage so that additional logic is not necessary for changing the
input polarity.
|
| IS_G_INVERTED |
BINARY |
1'b0 to 1'b1 |
1'b0 |
Specifies whether or not to use the optional inversion for the G pin of this component. |
| IS_PRE_INVERTED |
BINARY |
1'b0 to 1'b1 |
1'b0 |
Specifies whether or not to use the optional inversion for the PRE pin of this component. |
VHDL Instantiation Template
Verilog Instantiation Template