KEEPER - 2025.1 English - Primitive: I/O Weak Keeper - UG974

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2025-05-29
Version
2025.1 English

Primitive: I/O Weak Keeper

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: WEAK_DRIVER
  • Families: UltraScale, UltraScale+

Introduction

The design element is a weak keeper element that retains the value of the I/O when not being driven. For example, if a logic 1 is being driven onto the I/O, KEEPER drives a weak/resistive 1 onto the pin/port. If the net driver is then 3-stated, KEEPER continues to drive a weak/resistive 1 onto the pin/port.

Port Descriptions

Port Direction Width Function
O Inout 1 Keeper output. Connect directly to a top_level port.

Design Entry Method

Instantiation Yes
Inference Yes, via property
IP and IP Integrator Catalog No

VHDL Instantiation Template

Verilog Instantiation Template

Related Information