Introduction - Introduction - 2026.1 English - UG974

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2026-06-23
Version
2026.1 English

Overview

This HDL guide is part of the AMD Vivado™ Design Suite documentation collection.

This guide contains the following:

  • Introduction

  • Descriptions of each available macro

  • A list of design elements supported in this architecture, organized by functional categories

  • Descriptions of each available primitive

About Design Elements

This version of the Libraries Guide describes valid design elements for AMD UltraScale™ and AMD UltraScale+™ devices, and includes examples of instantiation code for each element. You can find the instantiation templates in a separate ZIP file, available at www.docs.amd.com (linked to this file) or within the Language Templates in the AMD Vivado™ Design Suite.

Design elements are divided into the following main categories:

  • Macros: These elements are in the Xilinx Parameterized Macro library in the tool, and are used to instantiate elements that are complex to instantiate using just the primitives. The synthesis tools will automatically expand the macros to their underlying primitives.

    Important: Unimacros from previous generation AMD FPGA architectures are not supported in the UltraScale and UltraScale+ architectures and have been replaced by Xilinx Parameterized Macros.

  • Primitives: Components that are native to the architecture you are targeting.

Design Entry Methods

For each design element in this guide, AMD, and recommends the best way to include the element in your design.

  • Instantiation: This component can be instantiated directly into the design. This method is useful to control the exact use, implementation, or placement of the individual blocks.
  • Inference:: This component can be inferred by most supported synthesis tools. Use this method for complete flexibility and portability of the code to multiple architectures. Inference also gives the tools the ability to optimize for performance, area, or power, as specified by the user to the synthesis tool.
  • IP catalog: This component can be instantiated from the IP catalog. The IP catalog maintains a library of IP Cores assembled from multiple primitives to form more complex functions, as well as interfaces to help in instantiation of the more complex primitives. References here to the IP catalog generally refer to when you use the IP catalog to assist in the use and integration of certain primitives into your design.