IBUFDS_IBUFDISABLE - 2025.1 English - Primitive: Differential Input Buffer With Input Buffer Disable - UG974

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2025-05-29
Version
2025.1 English

Primitive: Differential Input Buffer With Input Buffer Disable

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: INPUT_BUFFER
  • Families: UltraScale, UltraScale+

Introduction

This primitive is a differential input buffer with input disable for additional power savings when the input data is not needed. The USE_IBUFDISABLE attribute must be set to TRUE and the SIM_DEVICE to the appropriate value for this primitive to have the expected architecture specific behavior.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Port Descriptions

Port Direction Width Function
I Input 1 Diff_p Buffer Input. Connect to top-level p-side input port.
IB Input 1 Diff_n Buffer Input. Connect to top-level n-side input port.
IBUFDISABLE Input 1 Disables input path through the buffer and forces to a logic Low. This feature is generally used to reduce power at times when the I/O is idle for a period of time.
O Output 1 Buffer output

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
SIM_DEVICE STRING "ULTRASCALE", "ULTRASCALE_PLUS", "ULTRASCALE_PLUS_ES1", "ULTRASCALE_PLUS_ES2" "7SERIES" Set the device version for simulation functionality.
USE_IBUFDISABLE STRING "TRUE", "FALSE", "T_CONTROL" "TRUE" Set this attribute to "TRUE" to enable the IBUFDISABLE pin.

VHDL Instantiation Template

Verilog Instantiation Template

Related Information