IBUFDS_DIFF_OUT_INTERMDISABLE - 2025.1 English - Primitive: Differential Input Buffer with Complementary Outputs, Input Path Disable and On-die Input Termination Disable - UG974

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2025-05-29
Version
2025.1 English

Primitive: Differential Input Buffer with Complementary Outputs, Input Path Disable and On-die Input Termination Disable

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: INPUT_BUFFER
  • Families: UltraScale, UltraScale+

Introduction

The IBUFDS_DIFF_OUT_INTERMDISABLE primitive is available in the HR I/O banks. It has complementary differential outputs and a INTERMDISABLE port that can be used to manually disable the optional on-die receiver termination features (uncalibrated). See the UltraScale Architecture SelectIO Resources User Guide (UG571), "Uncalibrated Input Termination in I/O Banks" for more details. The USE_IBUFDISABLE attribute must be set to TRUE and SIM_DEVICE to the appropriate value for this primitive to have the expected behavior that is specific to the architecture.

If the I/O is using any on-die receiver termination features (uncalibrated), this primitive disables the termination legs whenever the INTERMDISABLE signal is asserted High.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Port Descriptions

Port Direction Width Function
I Input 1 Diff_p Buffer Input. Connect to top-level p-side input port.
IB Input 1 Diff_n Buffer Input. Connect to top-level n-side input port.
IBUFDISABLE Input 1 The IBUFDISABLE feature is not supported with this primitive in the UltraScale architecture. This port must be tied to logic '0'.
INTERMDISABLE Input 1 Disables input termination reducing current dissipation within the buffer. This feature is generally used to reduce power at times when the I/O is idle for a period of time.
O Output 1 Buffer diff_p output
OB Output 1 Buffer diff_n output

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
SIM_DEVICE STRING "ULTRASCALE", "ULTRASCALE_PLUS", "ULTRASCALE_PLUS_ES1", "ULTRASCALE_PLUS_ES2" "7SERIES" Set the device version for simulation functionality.
USE_IBUFDISABLE STRING "TRUE", "FALSE", "T_CONTROL" "TRUE" This attribute must be unspecified or set to "TRUE" if specified.

VHDL Instantiation Template

Verilog Instantiation Template

Related Information