IBUFDS - 2025.1 English - Primitive: Differential Input Buffer - UG974

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2025-05-29
Version
2025.1 English

Primitive: Differential Input Buffer

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: INPUT_BUFFER
  • Families: UltraScale, UltraScale+

Introduction

The usage and rules corresponding to the differential primitives are similar to the single-ended SelectIO primitives. Differential SelectIO primitives have two pins to and from the device pads to show the P and N channel pins in a differential pair. N channel pins have a B suffix.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Logic Table

Inputs Outputs
I IB O
0 0 No Change
0 1 0
1 0 1
1 1 No Change

Port Descriptions

Port Direction Width Function
I Input 1 Diff_p Buffer Input. Connect to top-level p-side input port.
IB Input 1 Diff_n Buffer Input. Connect to top-level n-side input port.
O Output 1 Buffer output

Design Entry Method

Instantiation Recommended
Inference No
IP and IP Integrator Catalog No

VHDL Instantiation Template

Verilog Instantiation Template

Related Information