IBUF - 2025.1 English - Primitive: Input Buffer - UG974

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2025-05-29
Version
2025.1 English

Primitive: Input Buffer

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: INPUT_BUFFER
  • Families: UltraScale, UltraScale+

Introduction

Single-ended signals used as simple inputs must use an input buffer (IBUF).

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Port Descriptions

Port Direction Width Function
I Input 1 Buffer input connected to a top-level input port.
O Output 1 Buffer output connected to internal device circuitry.

Design Entry Method

Instantiation Yes
Inference Recommended
IP and IP Integrator Catalog No

VHDL Instantiation Template

Verilog Instantiation Template

Related Information