Primitive: Digitally Controlled Impedance Reset Component
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: DCI_RESET
- Families: UltraScale, UltraScale+
Introduction
This design element is used to reset the digitally controlled impedance (DCI) state machine after configuration has been completed. By toggling the RST input to the DCIRESET primitive while the device is operating, the DCI state-machine is reset and both phases of impedance adjustment proceed in succession. All I/Os using DCI will be unavailable until the LOCKED output from the DCIRESET block is asserted.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| LOCKED | Output | 1 | DCI state-machine LOCK status output. When Low, DCI I/O impedance is being calibrated and DCI I/Os are unavailable. Upon a Low-to-High assertion, DCI I/Os are available for use. |
| RST | Input | 1 | Active-High asynchronous reset input to DCI state-machine. After RST is asserted, I/Os utilizing DCI will be unavailable until LOCKED is asserted. |
Design Entry Method
| Instantiation | Recommended |
| Inference | No |
| IP and IP Integrator Catalog | No |