Primitive: General Clock Buffer with Clock Enable
- PRIMITIVE_GROUP: CLOCK
- PRIMITIVE_SUBGROUP: BUFFER
- Families: UltraScale, UltraScale+
Introduction
This design element is a general clock buffer with a single gated
input. When clock enable (CE) is Low (inactive), its O output is 0.
When CE is High, the I input is transferred to the O
output.
Logic Table
| Inputs |
Outputs |
| I |
CE |
O |
| X |
0 |
0 |
| I |
1 |
I |
Port Descriptions
| Port |
Direction |
Width |
Function |
| CE |
Input |
1 |
Clock buffer active-High enable.
|
| I |
Input |
1 |
Buffer input.
|
| O |
Output |
1 |
Buffer output.
|
Design Entry Method
| Instantiation |
Recommended |
| Inference |
Yes |
| IP and IP Integrator Catalog |
No |
Available Attributes
| Attribute |
Type |
Allowed Values |
Default |
Description |
| CE_TYPE |
STRING |
"SYNC", "ASYNC", "HARDSYNC" |
"SYNC" |
Specifies whether the enable should be synchronous
(glitch-free) or asynchronous (no input clock switching
necessary). Versal devices have a an optional hardened
synchronizer circuit that can be enabled by using the
HARDSYNC setting. |
| IS_CE_INVERTED |
BINARY |
1'b0 to 1'b1 |
1'b0 |
Specifies use of the programmable inversion on the CE pin. |
| IS_I_INVERTED |
BINARY |
1'b0 to 1'b1 |
1'b0 |
Specifies use of the programmable inversion on the I pin. |
| SIM_DEVICE |
STRING |
"ULTRASCALE", "ULTRASCALE_PLUS",
"ULTRASCALE_PLUS_ES1", "ULTRASCALE_PLUS_ES2"
|
"ULTRASCALE" |
Set the device version |
VHDL Instantiation Template
Verilog Instantiation Template