Primitive: General Clock Buffer
- PRIMITIVE_GROUP: CLOCK
- PRIMITIVE_SUBGROUP: BUFFER
- Families: UltraScale, UltraScale+
Introduction
This design element is a high-fanout buffer that connects signals to the global routing resources for low-skew distribution of the signal. BUFGs are typically used on clock nets as well other high-fanout nets like sets, resets, and clock enables.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| I | Input | 1 | Clock input. |
| O | Output | 1 | Clock output. |
Design Entry Method
| Instantiation | Yes |
| Inference | Recommended |
| IP and IP Integrator Catalog | No |