XPM_NSU_MM - 2024.2 English - UG953

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2024-11-13
Version
2024.2 English

Parameterized Macro: NOC Slave Unit with memory mapped interface

  • MACRO_GROUP: XPM
  • MACRO_SUBGROUP: XPM_NOC

Introduction

This macro is used to instantiate NOC Slave Unit with memory mapped interface

Additionl content can go here.

Port Descriptions

Port Direction Width Domain Sense Handling if Unused Function
m_axi_aclk Input 1 NA EDGE_RISING Active AXI Interface master clock Clock signal. All inputs/outputs of this bus interface are rising edge aligned with this clock.
m_axi_araddr Output ADDR_WIDTH NA NA Active AXI Interface master araddr m_axi_araddr. Read address channel transaction address
m_axi_arburst Output 1 NA NA Active AXI Interface master arburst m_axi_arburst. Read address channel burst type code
m_axi_arcache Output 1 NA NA Active AXI Interface master arcache m_axi_arcache. Read address channel cache characteristics
m_axi_arid Output ID_WIDTH NA NA Active AXI Interface master arid m_axi_arid. Read address channel transaction id
m_axi_arlen Output 1 NA NA Active AXI Interface master arlen m_axi_arlen. Read address channel transaction burst length
m_axi_arlock Output 1 NA NA Active AXI Interface master arlock m_axi_arburst. Read address channel atomic access type
m_axi_arprot Output 1 NA NA Active AXI Interface master arprot m_axi_arprot. Read address channel region index
m_axi_arqos Output 1 NA NA Active AXI Interface master arprot m_axi_arqos. Read address channel quality of service
m_axi_arready Input 1 NA NA Active AXI Interface master bvalid m_axi_arready. Read address channel ready
m_axi_arregion Output 1 NA NA Active AXI Interface master arprot m_axi_arprot. Read address channel protection characteristics
m_axi_arsize Output 1 NA NA Active AXI Interface master arsize m_axi_arsize. Read address channel transfer size code
m_axi_aruser Output AUSER_WIDTH NA NA Active AXI Interface master aruser m_axi_aruser. Read address channel user-defined signals
m_axi_arvalid Output 1 NA NA Active AXI Interface master arvalid m_axi_arvalid. Read address channel valid
m_axi_awaddr Output ADDR_WIDTH NA NA Active AXI Interface master awaddr m_axi_awaddr. Write address channel transaction address
m_axi_awburst Output 1 NA NA Active AXI Interface master awburst m_axi_awburst. Write address channel burst type code
m_axi_awcache Output 1 NA NA Active AXI Interface master awcache m_axi_awcache. Write address channel cache characteristics
m_axi_awid Output ID_WIDTH NA NA Active AXI Interface master awid m_axi_awid. Write address channel transaction id
m_axi_awlen Output 1 NA NA Active AXI Interface master awlen m_axi_awlen. Write address channel transaction burst lengh
m_axi_awlock Output 1 NA NA Active AXI Interface master awlock m_axi_awlock. Write address channel atomic access type
m_axi_awprot Output 1 NA NA Active AXI Interface master awprot m_axi_awprot. Write address channel protection characteristics
m_axi_awqos Output 1 NA NA Active AXI Interface master awqos m_axi_awqos. Write address channel quality of service
m_axi_awready Input 1 NA NA Active AXI Interface master awready m_axi_awready. master write address ready
m_axi_awregion Output 1 NA NA Active AXI Interface master awregion m_axi_awregion. Write address channel region index
m_axi_awsize Output 1 NA NA Active AXI Interface master awsize m_axi_awsize. Write address channel transfer size code
m_axi_awuser Output AUSER_WIDTH NA NA Active AXI Interface master awuser m_axi_awprot. Write address channel user-defined signals
m_axi_awvalid Output 1 NA NA Active AXI Interface master awvalid m_axi_awprot. Write address channel valid
m_axi_bid Input ID_WIDTH NA NA Active AXI Interface master bid m_axi_bid. master write data response ID
m_axi_bready Output 1 NA NA Active AXI Interface master bready m_axi_bready. Write response channel ready
m_axi_bresp Input 1 NA NA Active AXI Interface master bresp m_axi_bid. master write response;
m_axi_buser Input 1 NA NA Active AXI Interface master buser m_axi_buser. Write response Channel user-defined signal
m_axi_bvalid Input 1 NA NA Active AXI Interface master bvalid m_axi_bvalid. Write response Channel valid
m_axi_out Output 1 NA NA Active Indicate AXI interface use
m_axi_rdata Input DATA_WIDTH NA NA Active AXI Interface master rdata m_axi_rdata. Read data channel data
m_axi_rid Input ID_WIDTH NA NA Active AXI Interface master rid m_axi_rid. Read data channel transaction id.
m_axi_rlast Input 1 NA NA Active AXI Interface master rlast m_axi_rlast. Read data channel last data beat
m_axi_rready Output 1 NA NA Active AXI Interface master rready m_axi_rready. Read data channel ready
m_axi_rresp Input 1 NA NA Active AXI Interface master rresp m_axi_rresp. Read data channel response code
m_axi_ruser Input DUSER_WIDTH NA NA Active AXI Interface master ruser m_axi_ruser. Read data channel user-defined signal
m_axi_rvalid Input 1 NA NA Active AXI Interface master rvalid m_axi_rvalid. Read data channel valid
m_axi_wdata Output DATA_WIDTH NA NA Active AXI Interface master wdata m_axi_wdata. Write data channel data
m_axi_wlast Output 1 NA NA Active AXI Interface master wlast m_axi_wlast. Write data channel last data beat
m_axi_wready Input 1 NA NA Active AXI Interface master awready m_axi_awready. master write data ready
m_axi_wstrb Output DATA_WIDTH / 8 NA NA Active AXI Interface master wstrb m_axi_wstrb. Write data channel byte strobes
m_axi_wuser Output DUSER_WIDTH NA NA Active AXI Interface master wuser m_axi_wuser. Write data channel user-defined signal
m_axi_wvalid Output 1 NA NA Active AXI Interface master wvalid m_axi_wvalid. Write data channel valid
nsu_usr_interrupt_in Input 1 NA NA Active User driven interrupt signal

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
ADDR_WIDTH DECIMAL 12 to 64 64 AXI channel Data width Allowd value 12 to 64 Default value = 64
AUSER_WIDTH DECIMAL 16, 18 16 VNOC AUSER User number 16 VNOC with parity disabled 18 VNOC with parity enabled
DATA_WIDTH DECIMAL 512, 32, 64, 128, 256 512 AXI channel Data width Allowd value 32,64,128,256,512 Default value = 512
DUSER_WIDTH DECIMAL 1, 2*DATA_WIDTH/8 1 VNOC DUSER User number 1 VNOC with parity disabled 2*DATA_WIDTH/8 VNOC with parity enabled
ENABLE_USR_INTERRUPT STRING "false", "true" "false" Enable user interrupt true Enable user interrupt functionality false Enable user interrupt functionality
ID_WIDTH DECIMAL 2 to 2 2 AXI Channel ID port width Allowed values 2 only
NOC_FABRIC STRING String "pl" Choosing the PL NMU of the given device
SIDEBAND_PINS STRING "false", "addr", "data", "true" "false" SIDEBAND pins true Drive AXI sideband parity signals over Address and Data User ports addr Drive AXI sideband parity signals over Address User ports data Drive AXI sideband parity signals over Data User ports false Disable driving AXI sideband parity signals over Address or Data User ports

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library xpm;
use xpm.vcomponents.all;

-- xpm_nsu_mm: NSU MM
-- Xilinx Parameterized Macro, version 2024.2


xpm_nsu_mm_inst : xpm_nsu_mm
 generic map (
			NOC_FABRIC => "pl", 			-- pl
			DATA_WIDTH => 512,     			-- 32/64/128/256/512
			ADDR_WIDTH => 64,      			-- 12 to 64
			ID_WIDTH => 2,     	  		-- always 2
			AUSER_WIDTH => 16,   			-- 16 for VNOC with parity disabled, 18 for VNOC with parity enabled
			DUSER_WIDTH => 1,       		-- 2*DATA_WIDTH/8 for parity enablement with VNOC, 1 for VNOC with parity disabled cases
			ENABLE_USR_INTERRUPT => "false",	-- false/true
			SIDEBAND_PINS => "false"		-- false/true/addr/data
) port map  (
			m_axi_aclk => m_axi_aclk,
			m_axi_awid => m_axi_awid,
			m_axi_awaddr => m_axi_awaddr,
			m_axi_awlen => m_axi_awlen,
			m_axi_awsize => m_axi_awsize,
			m_axi_awburst => m_axi_awburst,
			m_axi_awlock => m_axi_awlock,
			m_axi_awcache => m_axi_awcache,
			m_axi_awprot => m_axi_awprot,
			m_axi_awregion => m_axi_awregion,
			m_axi_awqos => m_axi_awqos,
			m_axi_awuser => m_axi_awuser,
			m_axi_awvalid => m_axi_awvalid,
			m_axi_awready => m_axi_awready,
			m_axi_wdata => m_axi_wdata,
			m_axi_wstrb => m_axi_wstrb,
			m_axi_wlast => m_axi_wlast,
			m_axi_wuser => m_axi_wuser,
			m_axi_wvalid => m_axi_wvalid,
			m_axi_wready => m_axi_wready,
			m_axi_bid => m_axi_bid,
			m_axi_bresp => m_axi_bresp,
			m_axi_buser => m_axi_buser, --supports only 16-bits transferred from NSU to NMU
			m_axi_bvalid => m_axi_bvalid,
			m_axi_bready => m_axi_bready,
			m_axi_arid => m_axi_arid,
			m_axi_araddr => m_axi_araddr,
			m_axi_arlen => m_axi_arlen,
			m_axi_arsize => m_axi_arsize,
			m_axi_arburst => m_axi_arburst,
			m_axi_arlock => m_axi_arlock,
			m_axi_arcache => m_axi_arcache,
			m_axi_arprot => m_axi_arprot,
			m_axi_arregion => m_axi_arregion,
			m_axi_arqos => m_axi_arqos,
			m_axi_aruser => m_axi_aruser,
			m_axi_arvalid => m_axi_arvalid,
			m_axi_arready => m_axi_arready,
			m_axi_rid => m_axi_rid,
			m_axi_rdata => m_axi_rdata,
			m_axi_rresp => m_axi_rresp,
			m_axi_rlast => m_axi_rlast,
			m_axi_ruser => m_axi_ruser,
			m_axi_rvalid => m_axi_rvalid,
			m_axi_rready => m_axi_rready,
			m_axi_out => m_axi_out,
			nsu_usr_interrupt_in => nsu_usr_interrupt_in
);
-- End of xpm_nsu_mm_inst instantiation

Verilog Instantiation Template


// xpm_nsu_mm: NSU MM
// Xilinx Parameterized Macro, version 2024.2


xpm_nsu_mm # (
	.NOC_FABRIC("pl"),		// pl
	.DATA_WIDTH(512),     		// 32/64/128/256/512
	.ADDR_WIDTH(64),      		// 12 to 64
	.ID_WIDTH(2),       		// always 2
	.AUSER_WIDTH(16), 		// 16 for VNOC with parity disabled, 18 for VNOC with parity enabled
	.DUSER_WIDTH(1),		// 2*DATA_WIDTH/8 for parity enablement with VNOC, 1 for VNOC with parity disabled cases
	.ENABLE_USR_INTERRUPT("false"), // false/true
	.SIDEBAND_PINS("false")		// false/true/addr/data
) xpm_nsu_mm_inst
 (
	.m_axi_aclk(m_axi_aclk),
	.m_axi_awid(m_axi_awid),
	.m_axi_awaddr(m_axi_awaddr),
	.m_axi_awlen(m_axi_awlen),
	.m_axi_awsize(m_axi_awsize),
	.m_axi_awburst(m_axi_awburst),
	.m_axi_awlock(m_axi_awlock),
	.m_axi_awcache(m_axi_awcache),
	.m_axi_awprot(m_axi_awprot),
	.m_axi_awregion(m_axi_awregion),
	.m_axi_awqos(m_axi_awqos),
	.m_axi_awuser(m_axi_awuser),
	.m_axi_awvalid(m_axi_awvalid),
	.m_axi_awready(m_axi_awready),
	.m_axi_wdata(m_axi_wdata),
	.m_axi_wstrb(m_axi_wstrb),
	.m_axi_wlast(m_axi_wlast),
	.m_axi_wuser(m_axi_wuser),
	.m_axi_wvalid(m_axi_wvalid),
	.m_axi_wready(m_axi_wready),
	.m_axi_bid(m_axi_bid),
	.m_axi_bresp(m_axi_bresp),
	.m_axi_buser(m_axi_buser), //supports only 16-bits transferred from NSU to NMU
	.m_axi_bvalid(m_axi_bvalid),
	.m_axi_bready(m_axi_bready),
	.m_axi_arid(m_axi_arid),
	.m_axi_araddr(m_axi_araddr),
	.m_axi_arlen(m_axi_arlen),
	.m_axi_arsize(m_axi_arsize),
	.m_axi_arburst(m_axi_arburst),
	.m_axi_arlock(m_axi_arlock),
	.m_axi_arcache(m_axi_arcache),
	.m_axi_arprot(m_axi_arprot),
	.m_axi_arregion(m_axi_arregion),
	.m_axi_arqos(m_axi_arqos),
	.m_axi_aruser(m_axi_aruser),
	.m_axi_arvalid(m_axi_arvalid),
	.m_axi_arready(m_axi_arready),
	.m_axi_rid(m_axi_rid),
	.m_axi_rdata(m_axi_rdata),
	.m_axi_rresp(m_axi_rresp),
	.m_axi_rlast(m_axi_rlast),
	.m_axi_ruser(m_axi_ruser),
	.m_axi_rvalid(m_axi_rvalid),
	.m_axi_rready(m_axi_rready),
	.m_axi_out(m_axi_out),
	.nsu_usr_interrupt_in(nsu_usr_interrupt_in)
);
// End of xpm_nsu_mm_inst instantiation