Parameterized Macro: NOC Master Unit with memory mapped interface
- MACRO_GROUP: XPM
- MACRO_SUBGROUP: XPM_NOC
Introduction
This macro is used to instantiate NOC Master Unit with memory mapped interface
Additionl content can go here.
Port Descriptions
Port | Direction | Width | Domain | Sense | Handling if Unused | Function |
---|---|---|---|---|---|---|
nmu_usr_interrupt_in | Input | 1 | NA | NA | Active | User driven interrupt signal |
s_axi_aclk | Input | 1 | NA | EDGE_RISING | Active | AXI Interface master clock Clock signal. All inputs/outputs of this bus interface are rising edge aligned with this clock. |
s_axi_araddr | Input | ADDR_WIDTH | NA | NA | Active | AXI Interface slave araddr s_axi_araddr. Read address channel transaction address |
s_axi_arburst | Input | 1 | NA | NA | Active | AXI Interface slave arburst s_axi_arburst. Read address channel burst type code |
s_axi_arcache | Input | 1 | NA | NA | Active | AXI Interface slave arcache s_axi_arcache. Read address channel cache characteristics |
s_axi_arid | Input | ID_WIDTH | NA | NA | Active | AXI Interface slave arid s_axi_arid. Read address channel transaction id |
s_axi_arlen | Input | 1 | NA | NA | Active | AXI Interface slave arlen s_axi_arlen. Read address channel transaction burst length |
s_axi_arlock | Input | 1 | NA | NA | Active | AXI Interface slave arlock s_axi_arburst. Read address channel atomic access type |
s_axi_arprot | Input | 1 | NA | NA | Active | AXI Interface slave arprot s_axi_arprot. Read address channel region index |
s_axi_arqos | Input | 1 | NA | NA | Active | AXI Interface slave arprot s_axi_arqos. Read address channel quality of service |
s_axi_arready | Output | 1 | NA | NA | Active | AXI Interface slave bvalid s_axi_arready. Read address channel ready |
s_axi_arregion | Input | 1 | NA | NA | Active | AXI Interface slave arprot s_axi_arprot. Read address channel protection characteristics |
s_axi_arsize | Input | 1 | NA | NA | Active | AXI Interface slave arsize s_axi_arsize. Read address channel transfer size code |
s_axi_aruser | Input | 1 | NA | NA | Active | AXI Interface slave aruser s_axi_aruser. Read address channel user-defined signals |
s_axi_arvalid | Input | 1 | NA | NA | Active | AXI Interface slave arvalid s_axi_arvalid. Read address channel valid |
s_axi_awaddr | Input | ADDR_WIDTH | NA | NA | Active | AXI Interface slave awaddr s_axi_awaddr. Write address channel transaction address |
s_axi_awburst | Input | 1 | NA | NA | Active | AXI Interface slave awburst s_axi_awburst. Write address channel burst type code |
s_axi_awcache | Input | 1 | NA | NA | Active | AXI Interface slave awcache s_axi_awcache. Write address channel cache characteristics |
s_axi_awid | Input | ID_WIDTH | NA | NA | Active | AXI Interface slave awid s_axi_awid. Write address channel transaction id |
s_axi_awlen | Input | 1 | NA | NA | Active | AXI Interface slave awlen s_axi_awlen. Write address channel transaction burst lengh |
s_axi_awlock | Input | 1 | NA | NA | Active | AXI Interface slave awlock s_axi_awlock. Write address channel atomic access type |
s_axi_awprot | Input | 1 | NA | NA | Active | AXI Interface slave awprot s_axi_awprot. Write address channel protection characteristics |
s_axi_awqos | Input | 1 | NA | NA | Active | AXI Interface slave awqos s_axi_awqos. Write address channel quality of service |
s_axi_awready | Input | 1 | NA | NA | Active | AXI Interface slave awready s_axi_awready. master write address ready |
s_axi_awregion | Input | 1 | NA | NA | Active | AXI Interface slave awregion s_axi_awregion. Write address channel region index |
s_axi_awsize | Input | 1 | NA | NA | Active | AXI Interface slave awsize s_axi_awsize. Write address channel transfer size code |
s_axi_awuser | Input | AUSER_WIDTH | NA | NA | Active | AXI Interface slave awuser s_axi_awprot. Write address channel user-defined signals |
s_axi_awvalid | Input | 1 | NA | NA | Active | AXI Interface slave awvalid s_axi_awprot. Write address channel valid |
s_axi_bid | Output | ID_WIDTH | NA | NA | Active | AXI Interface slave bid s_axi_bid. master write data response ID |
s_axi_bready | Input | 1 | NA | NA | Active | AXI Interface slave bready s_axi_bready. Write response channel ready |
s_axi_bresp | Output | 1 | NA | NA | Active | AXI Interface slave bresp s_axi_bid. master write response; |
s_axi_buser | Output | 1 | NA | NA | Active | AXI Interface slave buser s_axi_buser. Write response Channel user-defined signal |
s_axi_bvalid | Output | 1 | NA | NA | Active | AXI Interface slave bvalid s_axi_bvalid. Write response Channel valid |
s_axi_rdata | Output | DATA_WIDTH | NA | NA | Active | AXI Interface slave rdata s_axi_rdata. Read data channel data |
s_axi_rid | Output | ID_WIDTH | NA | NA | Active | AXI Interface master rid s_axi_rid. Read data channel transaction id. |
s_axi_rlast | Output | 1 | NA | NA | Active | AXI Interface slave rlast s_axi_rlast. Read data channel last data beat |
s_axi_rready | Input | 1 | NA | NA | Active | AXI Interface slave rready s_axi_rready. Read data channel ready |
s_axi_rresp | Output | 1 | NA | NA | Active | AXI Interface slave rresp s_axi_rresp. Read data channel response code |
s_axi_ruser | Output | DUSER_WIDTH | NA | NA | Active | AXI Interface slave ruser m_axi_ruser. Read data channel user-defined signal |
s_axi_rvalid | Output | 1 | NA | NA | Active | AXI Interface slave rvalid s_axi_rvalid. Read data channel valid |
s_axi_wdata | Input | DATA_WIDTH | NA | NA | Active | AXI Interface master wdata m_axi_wdata. Write data channel data |
s_axi_wid | Input | ID_WIDTH | NA | NA | Active | |
s_axi_wlast | Input | 1 | NA | NA | Active | AXI Interface slave wlast s_axi_wlast. Write data channel last data beat |
s_axi_wready | Output | 1 | NA | NA | Active | AXI Interface slave awready s_axi_awready. master write data ready |
s_axi_wstrb | Input | DATA_WDITH / 8 | NA | NA | Active | AXI Interface slave wstrb s_axi_wstrb. Write data channel byte strobes |
s_axi_wuser | Input | DUSER_WIDTH | NA | NA | Active | AXI Interface slave wuser s_axi_wuser. Write data channel user-defined signal |
s_axi_wvalid | Input | 1 | NA | NA | Active | AXI Interface master wvalid m_axi_wvalid. Write data channel valid |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
ADDR_WIDTH | DECIMAL | 12 to 64 | 64 | AXI channel Data width Allowd value 12 to 64 Default value = 64 |
AUSER_WIDTH | DECIMAL | 16, 18 | 16 | VNOC AUSER User number 16 VNOC with parity disabled 18 VNOC with parity enabled |
DATA_WIDTH | DECIMAL | 512, 32, 64, 128, 256 | 512 | AXI channel Data width Allowd value 32,64,128,256,512 Default value = 512 |
DUSER_WIDTH | DECIMAL | 1, 2*DATA_WIDTH/8 | 1 | VNOC DUSER User number 1 VNOC with parity disabled 2*DATA_WIDTH/8 VNOC with parity enabled |
ENABLE_USR_INTERRUPT | STRING | "false", "true" | "false" | Enable user interrupt true Enable user interrupt functionality false Enable user interrupt functionality |
ID_WIDTH | DECIMAL | 1 to 16 | 16 | AXI Channel ID port width Allowed values 2 only |
NOC_FABRIC | STRING | "pl", "pl_hbm" | "pl" | Choosing the PL NMU of the given device |
SIDEBAND_PINS | STRING | "false", "addr", "data", "true" | "false" | SIDEBAND pins true Drive AXI sideband parity signals over Address and Data User ports addr Drive AXI sideband parity signals over Address User ports data Drive AXI sideband parity signals over Data User ports false Disable driving AXI sideband parity signals over Address or Data User ports |
VHDL Instantiation Template
Unless they already exist, copy the
following two statements and paste them before the entity declaration.
Library xpm;
use xpm.vcomponents.all;
-- xpm_nmu_mm: NMU MM
-- Xilinx Parameterized Macro, version 2024.2
xpm_nmu_mm_inst : xpm_nmu_mm
generic map (
NOC_FABRIC => "pl", -- pl/pl_hbm
DATA_WIDTH => 512, -- 32/64/128/256/512
ADDR_WIDTH => 64, -- 12 to 64
ID_WIDTH => 16, -- 1 to 16
AUSER_WIDTH => 16, -- 16 for VNOC with parity disabled, 18 for VNOC with parity enabled
DUSER_WIDTH => 1, -- 2*DATA_WIDTH/8 for parity enablement with VNOC, 1 for VNOC with parity disabled cases
ENABLE_USR_INTERRUPT => "false", -- false/true
SIDEBAND_PINS => "false" -- false/true/addr/data
)
port map (
s_axi_aclk => s_axi_aclk,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awregion => s_axi_awregion,
s_axi_awqos => s_axi_awqos,
s_axi_awuser => s_axi_awuser,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wid => s_axi_wid,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wuser => s_axi_wuser,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_buser => s_axi_buser,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arregion => s_axi_arregion,
s_axi_arqos => s_axi_arqos,
s_axi_aruser => s_axi_aruser,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_ruser => s_axi_ruser,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
nmu_usr_interrupt_in => nmu_usr_interrupt_in
);
-- End of xpm_nmu_mm_inst instantiation
Verilog Instantiation Template
// xpm_nmu_mm: NMU MM
// Xilinx Parameterized Macro, version 2024.2
xpm_nmu_mm #(
.NOC_FABRIC("pl"), // pl/pl_hbm
.DATA_WIDTH(512), // 32/64/128/256/512
.ADDR_WIDTH(64), // 12 to 64
.ID_WIDTH(16), // 1 to 16
.AUSER_WIDTH(16), // 16 for VNOC with parity disabled, 18 for VNOC with parity enabled
.DUSER_WIDTH(1), // 2*DATA_WIDTH/8 for parity enablement with VNOC, 1 for VNOC with parity disabled cases
.ENABLE_USR_INTERRUPT("false"), // false/true
.SIDEBAND_PINS("false") //false/true/addr/data
)
xpm_nmu_mm_inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(s_axi_awuser),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(s_axi_wuser),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(s_axi_buser),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(s_axi_aruser),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(s_axi_ruser),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.nmu_usr_interrupt_in(nmu_usr_interrupt_in)
);
// End of xpm_nmu_mm_inst instantiation