XPM_MEMORY_SDPRAM - XPM_MEMORY_SDPRAM - 2026.1 English - Parameterized Macro: Simple Dual Port RAM

Parameterized Macro: Simple Dual Port RAM

MACRO_GROUP: XPM
MACRO_SUBGROUP: XPM_MEMORY

Introduction

This macro instantiates the Simple Dual Port RAM. Port A performs write operations to the memory and port B reads from the memory.

The following describes the basic read and write port usage of an XPM_MEMORY instance. It does not distinguish between port A and port B.

All synchronous signals are sensitive to the rising edge of clk[a|b], assumed to be a buffered and toggling clock signal behaving according to target device and memory primitive requirements.
A read operation is performed implicitly on address addrb combinatorially. The data output registers on each clkb cycle when enb is asserted.
Read data appears on the doutb port READ_LATENCY_B clkb cycles after the associated read operation.
A write operation is explicitly performed, writing dina to address addra, when both ena and wea are asserted on each clka cycle.
The value of en[a|b] gates all read and write operations on the initiating clk[a|b] cycle, regardless of input or output latencies. The addra and wea inputs have no effect when ena is deasserted on the coincident clk[a|b] cycle.
When rstb is asserted on a clkb cycle, the final output register resets immediately but synchronously to READ_RESET_VALUE_B, irrespective of READ_LATENCY_B.
When regceb is asserted and rstb is deasserted on a clkb cycle, the final output register captures and outputs the value from the previous pipeline register.
Undriven or unknown values provided on module inputs produce undefined memory array and output port behavior.
Using MEMORY INIT PARAM limits the maximum supported memory size to 4K bits.
Memory initialization with Asymmetric Byte Write Enable is not supported.
In Simple Dual Port RAM configuration, only WRITE_MODE_B is considered (though port A has the write permissions, WRITE_MODE_B is used because the output data will connect to port B, and the same mode value is applied to WRITE_MODE_A internally when passing to the primitive).
Choosing the Invalid Configuration results in a DRC.
For better timing performance in larger memories (>1 Mb), use CASCADE_HEIGHT of 1 with sufficient read latencies.

Note:

When the attribute “CLOCKING_MODE” is set to “common_clock”, all read/write operations to memory through port A and port B are performed on clka. If this attribute is set to “independent_clock”, then read/write operations through port A are performed based on clka, and read/write operations through port B are performed based on clkb.
Writing to an out-of-range address location may overwrite a valid address location when effective address bits match to a physical memory address location.
set_false_path constraint is needed for the independent clock distributed RAM based memory if the design takes care of avoiding address collision (write address != read address at any given point of time). Set USE_EMBEDDED_CONSTRAINT = 1 if XPM_MEMORY needs to take care of necessary constraints. If USE_EMBEDDED_CONSTRAINT = 0, Vivado may trigger Timing-6 or Timing-7 or both. Alternatively, you can also add the constraint when USE_EMBEDDED_CONSTRAINT = 0. An example of adding this constraint is provided below. If Port-B also has write permissions for an Independent clock configuration, then a similar constraint needs to be added for clkb as well.
```
set_false_path -from [filter [all_fanout -from [get_ports clka]
-flat -endpoints_only] {IS_LEAF}] -through [get_pins -of_objects
[get_cells -hier * -filter {PRIMITIVE_SUBGROUP==LUTRAM ||
PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==drom}]
-filter {DIRECTION==OUT}]
```
If"CLOCKING_MODE" is set to "independent_clock", Vivado may trigger a false positive CDC-1 warning and can be ignored.
The use of UltraRAM’s dedicated input and output registers are controlled by synthesis based on the READ_LATENCY_B value. For example, if 4 UltraRAMs are in cascade and the READ_LATENCY_B is ≥ 4, then synthesis will absorb as much registers inside UltraRAM primitive as possible.
For UltraRAM's, the enablement of OREG depends on the READ_LATENCY_B and WRITE_MODE_B. OREG enabled when READ_LATENCY_B ≥ 3 in READ_FIRST mode and READ_LATENCY_B ≥4 in WRITE_FIRST mode.
For larger memories (≥2 MB), use a read latency > 8 because the default cascade height used by Vivado synthesis is 8.

Timing Diagrams

Note: The UltraRAM primitive does not support Write/Read access in the clock cycle just before assertion of sleep gets recognized on the positive edge of the clock when its OREG attribute is set to TRUE. For UltraRAM configurations, Write/Read access to the memory is not allowed in the clock cycle just before the assertion of sleep.

ECC Modes

Both Block RAM and UltraRAM primitives support ECC when the memory type is set to Simple Dual Port RAM. The three ECC modes supported are:

Both encode and decode
Encode only
Decode only

The three ECC modes use the same read and write behavior described in the Introduction section above. Refer to the "Built-in Error Correction" section in the 7 Series FPGAs Memory Resources User Guide (UG473) for details on this feature like Error Injection and syndrome bits calculations.

Each ECC mode restricts the WRITE_DATA_WIDTH_A, READ_DATA_WIDTH_B, and MEMORY_SIZE attributes.

Both encode and decode WRITE_DATA_WIDTH_A and READ_DATA_WIDTH_B must be multiples of 64-bits. Violating this rule will results in a DRC in XPM_Memory.
Encode only WRITE_DATA_WIDTH_A must be a multiple of 64 bits and READ_DATA_WIDTH_B must be a multiple of 72-bits. MEMORY_SIZE must be a multiple of READ_DATA_WIDTH_B. Violating these rules will result in a DRC.
Decode only WRITE_DATA_WIDTH_A must be a multiple of 72 bits and READ_DATA_WIDTH_B must be a multiple of 64-bits. MEMORY_SIZE must be a multiple of WRITE_DATA_WIDTH_A. Violating these rules will result in a DRC.

ECC does not support the following:

Asymmetry
Initialization
Reset (neither non-zero reset value nor reset assertion)

Note: ECC uses a hard-ECC block available in the BRAM/URAM macro and the data width needs to be a multiple of 64/72. Use ECC IP for other data width combinations.

Auto Sleep Mode

This feature is applicable only when MEMORY_PRIMITIVE is URAM and is controlled internally in the UltraRAM to check if it can be put in sleep mode and when it needs to wake up. Thus power savings are obtained automatically without having to explicitly control the SLEEP Pin.
When AUTO_SLEEP_TIME is 0, the feature is disabled. When AUTO_SLEEP_TIME is non-zero, XPM_MEMORY constructs the pipeline registers equal to AUTO_SLEEP_TIME value on all input signals except rst[a|b].
If AUTO_SLEEP_TIME is too low, then UltraRAM goes into sleep and wakeup too often, which can cause more power to be consumed.
The number of sleep cycles achieved is calculated by following formula:
- If number of consecutive inactive cycles is < AUTO_SLEEP_TIME, then number of sleep cycles = 0.
- If number of consecutive inactive cycles is ≥AUTO_SLEEP_TIME, Then number of consecutive sleep cycles = Number of consecutive inactive cycles – 3.
- Inactive cycle is defined as a cycle where there is no Read/Write operation from either port.
The latency between the read operation and the data arrival at dout[a|b] is AUTO_SLEEP_TIME + READ_LATENCY_[A|B] clock cycles (Assuming that REGCE is high when the output data pipe line exists).
When the READ_LATENCY_[A|B] is set to 1 or 2, XPM_Memory behaviorally models the AUTO SLEEP feature and forces ‘x’ on DOUT[A|B] when the RAM is in Auto Sleep Mode. For READ_LATENCY_[A|B] greater than 2, the propagation of ‘x’ cannot happen to the DOUT[A|B] as the output registers gets the clock enable (delayed read enable) after UltraRAM comes out of sleep mode.
The Auto Sleep mode is most effective for larger memory sizes or any memory with very little activity.

Timing diagrams for Auto Sleep Mode at various read latencies are shown below.

Port Descriptions

Port	Direction	Width	Domain	Sense	Handling if Unused	Function
addra	Input	ADDR_WIDTH_A	clka	NA	Active	Address for port A write operations.
addrb	Input	ADDR_WIDTH_B	clkb	NA	Active	Address for port B read operations.
clka	Input	1	NA	EDGE_RISING	Active	Clock signal for port A. Also clocks port B when parameter CLOCKING_MODE is "common_clock".
clkb	Input	1	NA	EDGE_RISING	Active	Clock signal for port B when parameter CLOCKING_MODE is "independent_clock". Unused when parameter CLOCKING_MODE is "common_clock".
dbiterrb	Output	1	clkb	LEVEL_HIGH	DoNotCare	Status signal to indicate double bit error occurrence on the data output of port B.
dina	Input	WRITE_DATA_WIDTH_A	clka	NA	Active	Data input for port A write operations.
doutb	Output	READ_DATA_WIDTH_B	clkb	NA	Active	Data output for port B read operations.
ena	Input	1	clka	LEVEL_HIGH	Active	Memory enable signal for port A. Must be high on the clock cycles when you initiate write operations. Pipelined internally.
enb	Input	1	clkb	LEVEL_HIGH	Active	Memory enable signal for port B. Must be high on the clock cycles when you initiate read operations. Pipelined internally.
injectdbiterra	Input	1	clka	LEVEL_HIGH	0	Controls double bit error injection on input data when ECC enabled (Error injection capability is not available in "decode_only" mode).
injectsbiterra	Input	1	clka	LEVEL_HIGH	0	Controls single bit error injection on input data when ECC enabled (Error injection capability is not available in "decode_only" mode).
regceb	Input	1	clkb	LEVEL_HIGH	1	Clock Enable for the last register stage on the output data path.
rstb	Input	1	clkb	LEVEL_HIGH	Active	Reset signal for the final port B output register stage. Synchronously resets output port doutb to the value specified by parameter READ_RESET_VALUE_B.
sbiterrb	Output	1	clkb	LEVEL_HIGH	DoNotCare	Status signal to indicate single bit error occurrence on the data output of port B.
sleep	Input	1	NA	LEVEL_HIGH	0	sleep signal to enable the dynamic power saving feature.
wea	Input	WRITE_DATA_WIDTH_A / BYTE_WRITE_WIDTH_A	clka	LEVEL_HIGH	Active	Write enable vector for port A input data port dina. 1 bit wide for word-wide writes. In byte-wide write configurations, each bit controls the writing one byte of dina to address addra. For example, to synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A is 32, wea is 4'b0010.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
ADDR_WIDTH_A	DECIMAL	1 to 20	6	Specify the width of the port A address port addra, in bits. Must be large enough to access the entire memory from port A, that is, >= $clog2(MEMORY_SIZE/WRITE_DATA_WIDTH_A).
ADDR_WIDTH_B	DECIMAL	1 to 20	6	Specify the width of the port B address port addrb, in bits. Must be large enough to access the entire memory from port B, that is, >= $clog2(MEMORY_SIZE/READ_DATA_WIDTH_B).
AUTO_SLEEP_TIME	DECIMAL	0 to 15	0	Number of clk[a\|b] cycles to auto sleep, if feature is available in architecture. 0: Disable auto sleep feature 3-15: Number of auto sleep latency cycles Do not change from the value provided in the template instantiation.
BYTE_WRITE_WIDTH_A	DECIMAL	1 to 4608	32	To enable byte-wide writes on port A, specify the byte width, in bits. 8: 8-bit byte-wide writes, legal when WRITE_DATA_WIDTH_A is an integer multiple of 8 9: 9-bit byte-wide writes, legal when WRITE_DATA_WIDTH_A is an integer multiple of 9 Or to enable word-wide writes on port A, specify the same value as for WRITE_DATA_WIDTH_A.
CASCADE_HEIGHT	DECIMAL	0 to 64	0	0: No Cascade Height: Enables Vivado Synthesis to choose. 1 or more: Vivado Synthesis sets the specified value as Cascade Height.
CLOCKING_MODE	STRING	"common_clock", "independent_clock"	"common_clock"	Specifies whether port A and port B use a common clock or independent clocks. "common_clock": Common clocking; clock both port A and port B with clka "independent_clock": Independent clocking; clock port A with clka and port B with clkb
ECC_BIT_RANGE	STRING	String	"7:0"	This parameter is only used by synthesis. Specify the ECC bit range on the provided data. "7:0": it specifies lower 8 bits are ECC bits.
ECC_MODE	STRING	"no_ecc", "both_encode_and_decode", "decode_only", "encode_only"	"no_ecc"	"no_ecc": Disables ECC "encode_only": Enables ECC Encoder only "decode_only": Enables ECC Decoder only "both_encode_and_decode": Enables both ECC Encoder and Decoder
ECC_TYPE	STRING	"none", "ECCHSIAO32-7", "ECCHSIAO64-8", "ECCHSIAO128-9", "ECCH32-7", "ECCH64-8"	"none"	This parameter is only used by synthesis. Specify the algorithm used to generate the ecc bits outside the XPM Memory. XPM Memory does not performs ECC operation with this parameter. When ECC_MODE is not equal to no_ecc, the macro ignores the ECC_TYPE parameter and sets its value to none. "none": No ECC "ECCH32-7": Uses 32 bit ECC Hamming algorithm "ECCH64-8": Uses 64 bit ECC Hamming algorithm "ECCHSIAO32-7": Uses 32 bit ECC HSIAO algorithm "ECCHSIAO64-8": Uses 64 bit ECC HSIAO algorithm "ECCHSIAO128-9": Uses 128 bit ECC HSIAO algorithm
IGNORE_INIT_SYNTH	DECIMAL	0 to 1	0	0: Initiazation file if specified applies for both simulation and synthesis 1: Initiazation file if specified applies for only simulation and ignored for synthesis
MEMORY_INIT_FILE	STRING	String	"none"	Specify "none" (including quotes) for no memory initialization, or specify the name of a memory initialization file. Enter only the name of the file with .mem extension, including quotes but without path (for example, "my_file.mem"). File format must be ASCII and consist of only hexadecimal values organized into the specified depth by narrowest data width generic value of the memory. Initialization of memory happens through the file name specified only when parameter MEMORY_INIT_PARAM value is equal to "". When using XPM_MEMORY in a project, add the specified file to the Vivado project as a design source.
MEMORY_INIT_PARAM	STRING	String	"0"	Specify "" or "0" (including quotes) for no memory initialization through parameter, or specify the string containing the hex characters. Enter only hex characters with each location separated by delimiter (,). Parameter format must be ASCII and consist of only hexadecimal values organized into the specified depth by narrowest data width generic value of the memory. For example, if the narrowest data width is 8, and the depth of memory is 8 locations, then pass the parameter value as follows. parameter MEMORY_INIT_PARAM = "AB,CD,EF,1,2,34,56,78" Where "AB" is the 0th location and "78" is the 7th location.
MEMORY_OPTIMIZATION	STRING	"true", "false"	"true"	Specify "true" to enable the optimization of unused memory or bits in the memory structure. Specify "false" to disable the optimization of unused memory or bits in the memory structure
MEMORY_PRIMITIVE	STRING	"auto", "block", "distributed", "mixed", "ultra"	"auto"	Specifies the memory primitive (resource type) to use. "auto": Enables Vivado Synthesis to choose "distributed": Distributed memory "block": Block memory "ultra": UltraRAM memory "mixed": Mixed memory NOTE: Selecting Block RAM or UltraRAM specific features, like ECC or Asymmetry, with MEMORY_PRIMITIVE set to "auto" might cause a behavior mismatch.
MEMORY_SIZE	DECIMAL	2 to 150994944	2048	Specify the total memory array size, in bits. For example, enter 65536 for a 2kx32 RAM. When you enable ECC and set it to "encode_only", then the memory size has to be multiples of READ_DATA_WIDTH_B When you enable ECC and set it to "decode_only", then the memory size has to be multiples of WRITE_DATA_WIDTH_A
MESSAGE_CONTROL	DECIMAL	0 to 1	0	Specify 1 to enable the dynamic message reporting such as collision warnings, and 0 to disable the message reporting
RAM_DECOMP	STRING	"auto", "area", "power"	"auto"	Specifies the decomposition of the memory. "auto": Synthesis selects default. "power": Synthesis selects a strategy to reduce switching activity of RAMs and maps using widest configuration possible. "area": Synthesis selects a strategy to reduce RAM resource count.
READ_DATA_WIDTH_B	DECIMAL	1 to 4608	32	Specify the width of the port B read data output port doutb, in bits. When you enable ECC and set it to "encode_only", then READ_DATA_WIDTH_B has to be multiples of 72-bits When you enable ECC and set it to "decode_only" or "both_encode_and_decode", then READ_DATA_WIDTH_B has to be multiples of 64-bits
READ_LATENCY_B	DECIMAL	0 to 100	2	Specify the number of register stages in the port B read data pipeline. Read data output to port doutb takes this number of clkb cycles (clka when CLOCKING_MODE is "common_clock"). Targeting block memory requires a value of 1 or larger; 1 causes use of memory latch only; 2 causes use of output register. Targeting distributed memory requires a value of 0 or larger; 0 indicates combinatorial output. Values larger than 2 synthesize additional flip-flops that are not retimed into memory primitives.
READ_RESET_VALUE_B	STRING	String	"0"	Specify the reset value of the port B final output register stage in response to rstb input port assertion. As this parameter is a string, specify the hex values inside double quotes. As an example, If the read data width is 8, then specify READ_RESET_VALUE_B = "EA"; When you enable ECC, reset value is not supported.
RST_MODE_A	STRING	"SYNC", "ASYNC"	"SYNC"	Describes the behavior of the reset "SYNC": when you apply reset, it synchronously resets output port douta to the value specified by parameter READ_RESET_VALUE_A "ASYNC": when you apply reset, it asynchronously resets output port douta to zero
RST_MODE_B	STRING	"SYNC", "ASYNC"	"SYNC"	Describes the behavior of the reset "SYNC": When you apply reset, it synchronously resets output port doutb to the value specified by parameter READ_RESET_VALUE_B "ASYNC": When you apply reset, it asynchronously resets output port doutb to zero
SIM_ASSERT_CHK	DECIMAL	0 to 1	0	0: Disable simulation message reporting. This does not report messages related to potential misuse. 1: Enable simulation message reporting. This reports messages related to potential misuse.
USE_EMBEDDED_CONSTRAINT	DECIMAL	0 to 1	0	Specify 1 to enable the set_false_path constraint addition between clka of Distributed RAM and doutb_reg on clkb
USE_MEM_INIT	DECIMAL	0 to 1	1	Specify 1 to enable the generation of the following message and 0 to disable generation of the following message completely. "INFO - MEMORY_INIT_FILE and MEMORY_INIT_PARAM together specifies no memory initialization. Initial memory contents will be all 0s." NOTE: The message generates only when there is no Memory Initialization specified either through file or parameter.
USE_MEM_INIT_MMI	DECIMAL	0 to 1	0	Specify 1 to expose this memory information for writing to the MMI file.
WAKEUP_TIME	STRING	"disable_sleep", "use_sleep_pin"	"disable_sleep"	Specify "disable_sleep" to disable dynamic power saving option, and specify "use_sleep_pin" to enable the dynamic power saving option
WRITE_DATA_WIDTH_A	DECIMAL	1 to 4608	32	Specify the width of the port A write data input port dina, in bits. The values of WRITE_DATA_WIDTH_A and READ_DATA_WIDTH_A must be equal. When you enable ECC and set it to "encode_only" or "both_encode_and_decode", then WRITE_DATA_WIDTH_A must be multiples of 64-bits. When you enable ECC and set it to "decode_only", then WRITE_DATA_WIDTH_A must be multiples of 72-bits.
WRITE_MODE_B	STRING	"no_change", "read_first", "write_first"	"no_change"	Write mode behavior for port B output data port, doutb. When you set MEMORY_PRIMITIVE to Distributed memory, the only supported WRITE_MODE_B value is READ_FIRST When you set MEMORY_PRIMITIVE to Block memory, the only supported WRITE_MODE_B values are READ_FIRST and NO_CHANGE When you set MEMORY_PRIMITIVE to UltraRAM memory, the only supported WRITE_MODE_B values are READ_FIRST and WRITE_FIRST
WRITE_PROTECT	DECIMAL	0 to 1	1	This setting defaults to 1. This setting requires enable and write enable to protect write operations and places the LUT before the memory. This configuration provides the default memory access behavior. When 0, this setting disables write protection and connects write enable (WE) directly to memory. NOTE: Disable this option only if advanced users can guarantee they never assert write enable (WE) without enable (EN).

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library xpm;
use xpm.vcomponents.all;


-- xpm_memory_sdpram: Simple Dual Port RAM
-- Xilinx Parameterized Macro, version 2026.1

xpm_memory_sdpram_inst : xpm_memory_sdpram
generic map (
   ADDR_WIDTH_A => 6,               -- DECIMAL
   ADDR_WIDTH_B => 6,               -- DECIMAL
   AUTO_SLEEP_TIME => 0,            -- DECIMAL
   BYTE_WRITE_WIDTH_A => 32,        -- DECIMAL
   CASCADE_HEIGHT => 0,             -- DECIMAL
   CLOCKING_MODE => "common_clock", -- String
   ECC_BIT_RANGE => "7:0",          -- String
   ECC_MODE => "no_ecc",            -- String
   ECC_TYPE => "none",              -- String
   IGNORE_INIT_SYNTH => 0,          -- DECIMAL
   MEMORY_INIT_FILE => "none",      -- String
   MEMORY_INIT_PARAM => "0",        -- String
   MEMORY_OPTIMIZATION => "true",   -- String
   MEMORY_PRIMITIVE => "auto",      -- String
   MEMORY_SIZE => 2048,             -- DECIMAL
   MESSAGE_CONTROL => 0,            -- DECIMAL
   RAM_DECOMP => "auto",            -- String
   READ_DATA_WIDTH_B => 32,         -- DECIMAL
   READ_LATENCY_B => 2,             -- DECIMAL
   READ_RESET_VALUE_B => "0",       -- String
   RST_MODE_A => "SYNC",            -- String
   RST_MODE_B => "SYNC",            -- String
   SIM_ASSERT_CHK => 0,             -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
   USE_EMBEDDED_CONSTRAINT => 0,    -- DECIMAL
   USE_MEM_INIT => 1,               -- DECIMAL
   USE_MEM_INIT_MMI => 0,           -- DECIMAL
   WAKEUP_TIME => "disable_sleep",  -- String
   WRITE_DATA_WIDTH_A => 32,        -- DECIMAL
   WRITE_MODE_B => "no_change",     -- String
   WRITE_PROTECT => 1               -- DECIMAL
)
port map (
   sleep => sleep, -- 1-bit input: sleep signal to enable the dynamic power saving feature.
   clka => clka, -- 1-bit input: Clock signal for port A. Also clocks port B when parameter CLOCKING_MODE is "common_clock".
   ena => ena, -- 1-bit input: Memory enable signal for port A. Must be high on the clock cycles when you initiate write
                                     -- operations. Pipelined internally.

   wea => wea, -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector for port A input data port dina. 1
                                     -- bit wide for word-wide writes. In byte-wide write configurations, each bit controls the writing one byte
                                     -- of dina to address addra. For example, to synchronously write only bits [15-8] of dina when
                                     -- WRITE_DATA_WIDTH_A is 32, wea is 4'b0010.

   addra => addra, -- ADDR_WIDTH_A-bit input: Address for port A write operations.
   dina => dina, -- WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
   injectsbiterra => injectsbiterra, -- 1-bit input: Controls single bit error injection on input data when ECC enabled (Error injection
                                     -- capability is not available in "decode_only" mode).

   injectdbiterra => injectdbiterra, -- 1-bit input: Controls double bit error injection on input data when ECC enabled (Error injection
                                     -- capability is not available in "decode_only" mode).

   clkb => clkb, -- 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is "independent_clock". Unused when
                                     -- parameter CLOCKING_MODE is "common_clock".

   rstb => rstb, -- 1-bit input: Reset signal for the final port B output register stage. Synchronously resets output port
                                     -- doutb to the value specified by parameter READ_RESET_VALUE_B.

   enb => enb, -- 1-bit input: Memory enable signal for port B. Must be high on the clock cycles when you initiate read
                                     -- operations. Pipelined internally.

   regceb => regceb, -- 1-bit input: Clock Enable for the last register stage on the output data path.
   addrb => addrb, -- ADDR_WIDTH_B-bit input: Address for port B read operations.
   doutb => doutb, -- READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
   sbiterrb => sbiterrb, -- 1-bit output: Status signal to indicate single bit error occurrence on the data output of port B.
   dbiterrb => dbiterrb -- 1-bit output: Status signal to indicate double bit error occurrence on the data output of port B.
);

-- End of xpm_memory_sdpram_inst instantiation

Verilog Instantiation Template


// xpm_memory_sdpram: Simple Dual Port RAM
// Xilinx Parameterized Macro, version 2026.1

xpm_memory_sdpram #(
   .ADDR_WIDTH_A(6),               // DECIMAL
   .ADDR_WIDTH_B(6),               // DECIMAL
   .AUTO_SLEEP_TIME(0),            // DECIMAL
   .BYTE_WRITE_WIDTH_A(32),        // DECIMAL
   .CASCADE_HEIGHT(0),             // DECIMAL
   .CLOCKING_MODE("common_clock"), // String
   .ECC_BIT_RANGE("7:0"),          // String
   .ECC_MODE("no_ecc"),            // String
   .ECC_TYPE("none"),              // String
   .IGNORE_INIT_SYNTH(0),          // DECIMAL
   .MEMORY_INIT_FILE("none"),      // String
   .MEMORY_INIT_PARAM("0"),        // String
   .MEMORY_OPTIMIZATION("true"),   // String
   .MEMORY_PRIMITIVE("auto"),      // String
   .MEMORY_SIZE(2048),             // DECIMAL
   .MESSAGE_CONTROL(0),            // DECIMAL
   .RAM_DECOMP("auto"),            // String
   .READ_DATA_WIDTH_B(32),         // DECIMAL
   .READ_LATENCY_B(2),             // DECIMAL
   .READ_RESET_VALUE_B("0"),       // String
   .RST_MODE_A("SYNC"),            // String
   .RST_MODE_B("SYNC"),            // String
   .SIM_ASSERT_CHK(0),             // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
   .USE_EMBEDDED_CONSTRAINT(0),    // DECIMAL
   .USE_MEM_INIT(1),               // DECIMAL
   .USE_MEM_INIT_MMI(0),           // DECIMAL
   .WAKEUP_TIME("disable_sleep"),  // String
   .WRITE_DATA_WIDTH_A(32),        // DECIMAL
   .WRITE_MODE_B("no_change"),     // String
   .WRITE_PROTECT(1)               // DECIMAL
)
xpm_memory_sdpram_inst (
   .sleep(sleep), // 1-bit input: sleep signal to enable the dynamic power saving feature.
   .clka(clka), // 1-bit input: Clock signal for port A. Also clocks port B when parameter CLOCKING_MODE is "common_clock".
   .ena(ena), // 1-bit input: Memory enable signal for port A. Must be high on the clock cycles when you initiate write
                                    // operations. Pipelined internally.

   .wea(wea), // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector for port A input data port dina. 1 bit
                                    // wide for word-wide writes. In byte-wide write configurations, each bit controls the writing one byte of
                                    // dina to address addra. For example, to synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
                                    // is 32, wea is 4'b0010.

   .addra(addra), // ADDR_WIDTH_A-bit input: Address for port A write operations.
   .dina(dina), // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
   .injectsbiterra(injectsbiterra), // 1-bit input: Controls single bit error injection on input data when ECC enabled (Error injection capability
                                    // is not available in "decode_only" mode).

   .injectdbiterra(injectdbiterra), // 1-bit input: Controls double bit error injection on input data when ECC enabled (Error injection capability
                                    // is not available in "decode_only" mode).

   .clkb(clkb), // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is "independent_clock". Unused when
                                    // parameter CLOCKING_MODE is "common_clock".

   .rstb(rstb), // 1-bit input: Reset signal for the final port B output register stage. Synchronously resets output port
                                    // doutb to the value specified by parameter READ_RESET_VALUE_B.

   .enb(enb), // 1-bit input: Memory enable signal for port B. Must be high on the clock cycles when you initiate read
                                    // operations. Pipelined internally.

   .regceb(regceb), // 1-bit input: Clock Enable for the last register stage on the output data path.
   .addrb(addrb), // ADDR_WIDTH_B-bit input: Address for port B read operations.
   .doutb(doutb), // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
   .sbiterrb(sbiterrb), // 1-bit output: Status signal to indicate single bit error occurrence on the data output of port B.
   .dbiterrb(dbiterrb) // 1-bit output: Status signal to indicate double bit error occurrence on the data output of port B.
);

// End of xpm_memory_sdpram_inst instantiation

XPM_MEMORY_SDPRAM - XPM_MEMORY_SDPRAM - 2026.1 English - Parameterized Macro: Simple Dual Port RAM - UG953

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)