ROM32X1 - ROM32X1 - 2026.1 English - Primitive: 32-Deep by 1-Wide ROM

Primitive: 32-Deep by 1-Wide ROM

PRIMITIVE_GROUP: CLB
PRIMITIVE_SUBGROUP: ROM

Introduction

This design element is a 32-word by 1-bit read-only memory. The data output (O) reflects the word selected by the 5-bit address (A4:A0). The INIT parameter initializes the ROM to a known value during configuration. The value consists of eight hexadecimal digits written into the ROM from the most-significant digit A=1FH to the least-significant digit A=00H.

For example, INIT=10A78F39 produces the data stream: 0001 0000 1010 0111 1000 1111 0011 1001.

If you do not specify the INIT parameter, an error occurs.

Logic Table

Input				Output
I0	I1	I2	I3	O
0	0	0	0	INIT(0)
0	0	0	1	INIT(1)
0	0	1	0	INIT(2)
0	0	1	1	INIT(3)
0	1	0	0	INIT(4)
0	1	0	1	INIT(5)
0	1	1	0	INIT(6)
0	1	1	1	INIT(7)
1	0	0	0	INIT(8)
1	0	0	1	INIT(9)
1	0	1	0	INIT(10)
1	0	1	1	INIT(11)
1	1	0	0	INIT(12)
1	1	0	1	INIT(13)
1	1	1	0	INIT(14)
1	1	1	1	INIT(15)

Design Entry Method

Instantiation	Yes
Inference	Recommended
IP catalog	No
Macro support	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
INIT	HEX	Any 32-Bit Value	All zeros	Specifies the contents of the ROM.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- ROM32X1: 32 x 1 Asynchronous Distributed (LUT) ROM
--          7 Series
-- Xilinx HDL Language Template, version 2026.1

ROM32X1_inst : ROM32X1
generic map (
   INIT => X"00000000")
port map (
   O => O,   -- ROM output
   A0 => A0, -- ROM address[0]
   A1 => A1, -- ROM address[1]
   A2 => A2, -- ROM address[2]
   A3 => A3, -- ROM address[3]
   A4 => A4  -- ROM address[4]
);
-- End of ROM32X1_inst instantiation

Verilog Instantiation Template


// ROM32X1: 32 x 1 Asynchronous Distributed (LUT) ROM (Mapped to a SliceM LUT6)
//          7 Series
// Xilinx HDL Language Template, version 2026.1

ROM32X1 #(
   .INIT(32'h00000000) // Contents of ROM
) ROM32X1_inst (
   .O(O),   // ROM output
   .A0(A0), // ROM address[0]
   .A1(A1), // ROM address[1]
   .A2(A2), // ROM address[2]
   .A3(A3), // ROM address[3]
   .A4(A4)  // ROM address[4]
);

// End of ROM32X1_inst instantiation

Related Information

7 Series FPGAs Configurable Logic Block User Guide (UG474)

ROM32X1 - ROM32X1 - 2026.1 English - Primitive: 32-Deep by 1-Wide ROM - UG953