The following Primitive Groups correlate to the PRIMTIVE_GROUP cell property in the Vivado software. Similarly, the listed Primitive Subgroup correlates to the PRIMTIVE_SUBGROUP property on the cells in the software. These can be used in filters to specify a class of cells for constraint processing and other tasks within Vivado.
ADVANCED
| Design Element | Description | Primitive Subgroup |
|---|---|---|
| IBUFDS_GTE2 | Primitive: Gigabit Transceiver Buffer | GT |
| XADC | Primitive: Dual 12-Bit 1MSPS Analog-to-Digital Converter | ADC |
ARITHMETIC
| Design Element | Description | Primitive Subgroup |
|---|---|---|
| DSP48E1 | Primitive: 48-bit Multi-Functional Arithmetic Block | DSP |
BLOCKRAM
| Design Element | Description | Primitive Subgroup |
|---|---|---|
| FIFO18E1 | Primitive: 18Kb FIFO (First-In-First-Out) Block RAM Memory | FIFO |
| FIFO36E1 | Primitive: 36 Kb FIFO (First-In-First-Out) Block RAM Memory | FIFO |
| RAMB18E1 | Primitive: 18K-bit Configurable Synchronous Block RAM | BRAM |
| RAMB36E1 | Primitive: 36K-bit Configurable Synchronous Block RAM | BRAM |
CLB
| Design Element | Description | Primitive Subgroup |
|---|---|---|
| CARRY4 | Primitive: Fast Carry Logic with Look Ahead | CARRY |
| CFGLUT5 | Primitive: 5-input Dynamically Reconfigurable Look-Up Table (LUT) | LUT |
| LUT1 | Primitive: 1-Bit Look-Up Table | LUT |
| LUT2 | Primitive: 2-Bit Look-Up Table | LUT |
| LUT3 | Primitive: 3-Bit Look-Up Table | LUT |
| LUT4 | Primitive: 4-Bit Look-Up Table | LUT |
| LUT5 | Primitive: 5-Bit Look-Up Table | LUT |
| LUT6 | Primitive: 6-Bit Look-Up Table | LUT |
| LUT6_2 | Primitive: 6-Bit Look-Up Table | LUT |
| MUXF7 | Primitive: CLB MUX to connect two LUT6's Together | MUXF |
| MUXF8 | Primitive: CLB MUX to connect two MUXF7's Together | MUXF |
| RAM128X1D | Primitive: 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM) | LUTRAM |
| RAM128X1S | Primitive: 128-Deep by 1-Wide Random Access Memory (Select RAM) | LUTRAM |
| RAM256X1S | Primitive: 256-Deep by 1-Wide Random Access Memory (Select RAM) | LUTRAM |
| RAM32M | Primitive: 32-Deep by 8-bit Wide Multi Port Random Access Memory (Select RAM) | LUTRAM |
| RAM32X1D | Primitive: 32-Deep by 1-Wide Static Dual Port Synchronous RAM | LUTRAM |
| RAM32X1S | Primitive: 32-Deep by 1-Wide Static Synchronous RAM | LUTRAM |
| RAM32X1S_1 | Primitive: 32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock | LUTRAM |
| RAM32X2S | Primitive: 32-Deep by 2-Wide Static Synchronous RAM | LUTRAM |
| RAM64M | Primitive: 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM) | LUTRAM |
| RAM64X1D | Primitive: 64-Deep by 1-Wide Dual Port Static Synchronous RAM | LUTRAM |
| RAM64X1S | Primitive: 64-Deep by 1-Wide Static Synchronous RAM | LUTRAM |
| RAM64X1S_1 | Primitive: 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock | LUTRAM |
| ROM128X1 | Primitive: 128-Deep by 1-Wide ROM | ROM |
| ROM256X1 | Primitive: 256-Deep by 1-Wide ROM | ROM |
| ROM32X1 | Primitive: 32-Deep by 1-Wide ROM | ROM |
| ROM64X1 | Primitive: 64-Deep by 1-Wide ROM | ROM |
| SRL16E | Primitive: 16-Bit Shift Register Look-Up Table (LUT) | SRL |
| SRLC32E | Primitive: 32-Bit Shift Register Look-Up Table (LUT) | SRL |
CLOCK
| Design Element | Description | Primitive Subgroup |
|---|---|---|
| BUFG | Primitive: General Clock Buffer | BUFFER |
| BUFGCE | Primitive: General Clock Buffer with Clock Enable | BUFFER |
| BUFGCE_1 | Primitive: General Clock Buffer with Clock Enable and Output State 1 | BUFFER |
| BUFGCTRL | Primitive: General Clock Control Buffer | MUX |
| BUFGMUX | Primitive: General Clock Mux Buffer | MUX |
| BUFGMUX_1 | Primitive: General Clock Mux Buffer with Output State 1 | MUX |
| BUFGMUX_CTRL | Primitive: 2-to-1 General Clock MUX Buffer | MUX |
| BUFH | Primitive: HROW Clock Buffer for a Single Clocking Region | BUFFER |
| BUFHCE | Primitive: HROW Clock Buffer for a Single Clocking Region with Clock Enable | BUFFER |
| BUFIO | Primitive: Local Clock Buffer for I/O | BUFFER |
| BUFMR | Primitive: Multi-Region Clock Buffer | BUFFER |
| BUFMRCE | Primitive: Multi-Region Clock Buffer with Clock Enable | BUFFER |
| BUFR | Primitive: Regional Clock Buffer for I/O and Logic Resources within a Clock Region | BUFFER |
| MMCME2_ADV | Primitive: Advanced Mixed Mode Clock Manager | PLL |
| MMCME2_BASE | Primitive: Base Mixed Mode Clock Manager | PLL |
| PLLE2_ADV | Primitive: Advanced Phase Locked Loop (PLL) | PLL |
| PLLE2_BASE | Primitive: Base Phase Locked Loop (PLL) | PLL |
CONFIGURATION
| Design Element | Description | Primitive Subgroup |
|---|---|---|
| BSCANE2 | Primitive: Boundary-Scan User Instruction | BSCAN |
| CAPTUREE2 | Primitive: Register Capture | CAPTURE |
| DNA_PORT | Primitive: Device DNA Access Port | DNA |
| EFUSE_USR | Primitive: 32-bit non-volatile design ID | EFUSE |
| FRAME_ECCE2 | Primitive: Configuration Frame Error Correction | ECC |
| ICAPE2 | Primitive: Internal Configuration Access Port | ICAP |
| STARTUPE2 | Primitive: STARTUP Block | STARTUP |
| USR_ACCESSE2 | Primitive: Configuration Data Access | USR_ACCESS |
I/O
| Design Element | Description | Primitive Subgroup |
|---|---|---|
| DCIRESET | Primitive: Digitally Controlled Impedance Reset Component | DCI_RESET |
| IBUF | Primitive: Input Buffer | INPUT_BUFFER |
| IBUF_IBUFDISABLE | Primitive: Input Buffer With Input Buffer Disable | INPUT_BUFFER |
| IBUF_INTERMDISABLE | Primitive: Input Buffer With Input Buffer Disable and On-die Input Termination Disable | INPUT_BUFFER |
| IBUFDS | Primitive: Differential Input Buffer | INPUT_BUFFER |
| IBUFDS_DIFF_OUT | Primitive: Differential Input Buffer With Complementary Outputs | INPUT_BUFFER |
| IBUFDS_DIFF_OUT_IBUFDISABLE | Primitive: Differential Input Buffer With Complementary Outputs and Input Buffer Disable | INPUT_BUFFER |
| IBUFDS_DIFF_OUT_INTERMDISABLE | Primitive: Differential Input Buffer with Complementary Outputs, Input Path Disable and On-die Input Termination Disable | INPUT_BUFFER |
| IBUFDS_IBUFDISABLE | Primitive: Differential Input Buffer With Input Buffer Disable | INPUT_BUFFER |
| IBUFDS_INTERMDISABLE | Primitive: Differential Input Buffer With Input Buffer Disable and On-die Input Termination Disable | INPUT_BUFFER |
| IDELAYCTRL | Primitive: IDELAYE3/ODELAYE3 Tap Delay Value Control | DELAY |
| IDELAYE2 | Primitive: Input Fixed or Variable Delay Element | DELAY |
| IN_FIFO | Primitive: Input First-In, First-Out (FIFO) | FIFO |
| IOBUF | Primitive: Input/Output Buffer | BIDIR_BUFFER |
| IOBUF_DCIEN | Primitive: Input/Output Buffer DCI Enable | BIDIR_BUFFER |
| IOBUF_INTERMDISABLE | Primitive: Bidirectional Buffer with Input Path Disable and On-die Input Termination Disable | BIDIR_BUFFER |
| IOBUFDS | Primitive: Differential Input/Output Buffer | BIDIR_BUFFER |
| IOBUFDS_DCIEN | Primitive: Differential Bidirectional Buffer With Input Buffer Disable and On-die Input Termination Disable | BIDIR_BUFFER |
| IOBUFDS_DIFF_OUT | Primitive: Differential Input/Output Buffer Primitive With Complementary Outputs for the Input Buffer | BIDIR_BUFFER |
| IOBUFDS_DIFF_OUT_DCIEN | Primitive: Differential Bidirectional Buffer with Complementary Outputs, Input Path Disable, and On-die Input Termination Disable | BIDIR_BUFFER |
| IOBUFDS_DIFF_OUT_INTERMDISABLE | Primitive: Differential Bidirectional Buffer with Complementary Outputs, Input Buffer Disable and On-die Input Termination Disable | BIDIR_BUFFER |
| IOBUFDS_INTERMDISABLE | Primitive: Differential Bidirectional Buffer With Input Buffer Disable and On-die Input | BIDIR_BUFFER |
| ISERDESE2 | Primitive: Input SERial/DESerializer with Bitslip | SERDES |
| KEEPER | Primitive: I/O Weak Keeper | WEAK_DRIVER |
| OBUF | Primitive: Output Buffer | OUTPUT_BUFFER |
| OBUFDS | Primitive: Differential Output Buffer | OUTPUT_BUFFER |
| OBUFT | Primitive: 3-State Output Buffer | OUTPUT_BUFFER |
| OBUFTDS | Primitive: Differential 3-state Output Buffer | OUTPUT_BUFFER |
| ODELAYE2 | Primitive: Output Fixed or Variable Delay Element | DELAY |
| OSERDESE2 | Primitive: Output SERial/DESerializer with bitslip | SERDES |
| OUT_FIFO | Primitive: Output First-In, First-Out (FIFO) Buffer | FIFO |
| PULLDOWN | Primitive: I/O Pulldown | WEAK_DRIVER |
| PULLUP | Primitive: I/O Pullup | WEAK_DRIVER |
REGISTER
| Design Element | Description | Primitive Subgroup |
|---|---|---|
| FDCE | Primitive: D Flip-Flop with Clock Enable and Asynchronous Clear | SDR |
| FDPE | Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset | SDR |
| FDRE | Primitive: D Flip-Flop with Clock Enable and Synchronous Reset | SDR |
| FDSE | Primitive: D Flip-Flop with Clock Enable and Synchronous Set | SDR |
| IDDR | Primitive: Input Double Data-Rate Register | DDR |
| IDDR_2CLK | Primitive: Input Double Data-Rate Register with Dual Clock Inputs | DDR |
| LDCE | Primitive: Transparent Latch with Clock Enable and Asynchronous Clear | LATCH |
| LDPE | Primitive: Transparent Latch with Clock Enable and Asynchronous Preset | LATCH |
| ODDR | Primitive: Dedicated Dual Data Rate (DDR) Output Register | DDR |