OBUFTDS - OBUFTDS - 2026.1 English - Primitive: Differential 3-state Output Buffer - UG953

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2026-06-23
Version
2026.1 English

Primitive: Differential 3-state Output Buffer

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: OUTPUT_BUFFER
Page-1 Graphic ID: SW & IP X13420 X13420-061219 Buffer.15 Sheet.3 I I Sheet.4 O O Sheet.5 OBUFTDS OBUFTDS Sheet.6 Sheet.7 Sheet.8 Sheet.9 Text Line.4 T T Sheet.11 OB OB O/P invert.50 Sheet.13 Sheet.14 Sheet.15 Sheet.16

Introduction

The OBUFTDS is a differential 3-state output buffer primitive.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD and SLEW, should be supplied to the top-level port via an appropriate property.

Logic Table

Inputs Outputs
I T O OB
X 1 Z Z
0 0 0 1
1 0 1 0

Port Descriptions

Port Direction Width Function
I Input 1 Buffer input.
O Output 1 Diff_p output. Connect directly to a top-level port in the design.
OB Output 1 Diff_n output. Connect directly to a top-level port in the design.
T Input 1 3-state enable input.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- OBUFTDS: Differential 3-state Output Buffer
--          7 Series
-- Xilinx HDL Language Template, version 2026.1

OBUFTDS_inst : OBUFTDS
generic map (
   IOSTANDARD => "DEFAULT")
port map (
   O => O,     -- Diff_p output (connect directly to top-level port)
   OB => OB,   -- Diff_n output (connect directly to top-level port)
   I => I,     -- Buffer input
   T => T      -- 3-state enable input
);

-- End of OBUFTDS_inst instantiation

Verilog Instantiation Template


// OBUFTDS: Differential 3-state Output Buffer
//          7 Series
// Xilinx HDL Language Template, version 2026.1

OBUFTDS #(
   .IOSTANDARD("DEFAULT"), // Specify the output I/O standard
   .SLEW("SLOW")           // Specify the output slew rate
) OBUFTDS_inst (
   .O(O),     // Diff_p output (connect directly to top-level port)
   .OB(OB),   // Diff_n output (connect directly to top-level port)
   .I(I),     // Buffer input
   .T(T)      // 3-state enable input
);

// End of OBUFTDS_inst instantiation

Related Information

  • 7 Series FPGAs SelectIO Resources User Guide (UG471)