Primitive: Output Buffer
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: OUTPUT_BUFFER
Introduction
An output buffer (OBUF) must be used to drive signals from the device to external output pads.
I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DRIVE, and SLEW, should be supplied to the top-level port via an appropriate property.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| I | Input | 1 | Input of OBUF. Connect to the logic driving the output port. |
| O | Output | 1 | Output of OBUF to be connected directly to top-level output port. |
Design Entry Method
| Instantiation | Yes |
| Inference | Recommended |
| IP and IP Integrator Catalog | No |
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- OBUF: Single-ended Output Buffer
-- 7 Series
-- Xilinx HDL Language Template, version 2026.1
OBUF_inst : OBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => O, -- Buffer output (connect directly to top-level port)
I => I -- Buffer input
);
-- End of OBUF_inst instantiation
Verilog Instantiation Template
// OBUF: Single-ended Output Buffer
// 7 Series
// Xilinx HDL Language Template, version 2026.1
OBUF #(
.DRIVE(12), // Specify the output drive strength
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
.SLEW("SLOW") // Specify the output slew rate
) OBUF_inst (
.O(O), // Buffer output (connect directly to top-level port)
.I(I) // Buffer input
);
// End of OBUF_inst instantiation
Related Information
- 7 Series FPGAs SelectIO Resources User Guide (UG471)