LUT6_2 - LUT6_2 - 2026.1 English - Primitive: 6-Bit Look-Up Table - UG953

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)
Document ID
UG953
Release Date
2026-06-23
Version
2026.1 English

Primitive: 6-Bit Look-Up Table

  • PRIMITIVE_GROUP: CLB
  • PRIMITIVE_SUBGROUP: LUT
Page-1 Sheet.1 LUT6_2 LUT6_2 Rectangle.129 LUT5 LUT5 Sheet.3 Mux 2:1 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Rectangle.3 LUT5 LUT5 Sheet.10 8pt. Arial Text.381 O6 O6 Sheet.12 8pt. Arial Text.16 I4 I4 8pt. Arial Text.17 I3 I3 8pt. Arial Text.18 I2 I2 Sheet.16 8pt. Arial Text.20 I1 I1 Sheet.18 8pt. Arial Text.22 I0 I0 Sheet.20 8pt. Arial Text.24 I4 I4 8pt. Arial Text.27 I3 I3 8pt. Arial Text.26 I2 I2 Sheet.24 8pt. Arial Text.30 I1 I1 8pt. Arial Text.31 I0 I0 Sheet.27 Sheet.28 Sheet.29 8pt. Arial Text.33 I5 I5 8pt. Arial Text.34 I4 I4 8pt. Arial Text.35 I3 I3 8pt. Arial Text.36 I2 I2 8pt. Arial Text.39 I1 I1 8pt. Arial Text.40 I0 I0 Sheet.36 Sheet.37 8pt. Arial Text.41 O5 O5 Sheet.39 Graphic ID: SW & IP X10961 X10961-061219

Introduction

This design element is a 6-input, 2-output look-up table (LUT) that acts either as a dual asynchronous 32-bit ROM (with 5-bit addressing), implements any two 5-input logic functions with shared inputs, or implements a 6-input logic function and a 5-input logic function with shared inputs and shared logic values. LUTs are the basic logic building blocks and implement most logic functions of the design. A LUT6_2 is be mapped to one of the four look-up tables in the slice. You must specify an INIT attribute consisting of a 64-bit hexadecimal value to indicate the LUT's logical function. The INIT value is calculated by assigning a 1 to corresponding INIT bit value when the associated inputs are applied. For instance, a Verilog INIT value of 64'hfffffffffffffffe (X"FFFFFFFFFFFFFFFE" for VHDL) makes the O6 output 1 unless all zeros are on the inputs and the O5 output a 1, or unless I[4:0] are all zeros (a 5-input and 6-input OR gate). The lower half (bits 31:0) of the INIT values apply to the logic function of the O5 output. The INIT parameter for the FPGA LUT primitive gives the LUT its logical value. By default, this value is zero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in most cases a new INIT value must be determined to specify the logic function for the LUT primitive the LUT value can be determined:
  • The Logic Table Method: A common method to determine the desired INIT value for a LUT is using a logic table. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of the output and then create the INIT string from those output values.
  • The Equation Method: Another method to determine the LUT value is to define parameters or generics for each input to the LUT that correspond to their listed truth value and use those to build the logic equation you are after. This method is easier to understand once you have grasped the concept and is more self-documenting than the above method. However, this method does require the code to first specify the appropriate parameters or generics.

Logic Table

Inputs Outputs
I5 I4 I3 I2 I1 I0 O5 O6
0 0 0 0 0 0 INIT[0] INIT[0]
0 0 0 0 0 1 INIT[1] INIT[1]
0 0 0 0 1 0 INIT[2] INIT[2]
0 0 0 0 1 1 INIT[3] INIT[3]
0 0 0 1 0 0 INIT[4] INIT[4]
0 0 0 1 0 1 INIT[5] INIT[5]
0 0 0 1 1 0 INIT[6] INIT[6]
0 0 0 1 1 1 INIT[7] INIT[7]
0 0 1 0 0 0 INIT[8] INIT[8]
0 0 1 0 0 1 INIT[9] INIT[9]
0 0 1 0 1 0 INIT[10] INIT[10]
0 0 1 0 1 1 INIT[11] INIT[11]
0 0 1 1 0 0 INIT[12] INIT[12]
0 0 1 1 0 1 INIT[13] INIT[13]
0 0 1 1 1 0 INIT[14] INIT[14]
0 0 1 1 1 1 INIT[15] INIT[15]
0 1 0 0 0 0 INIT[16] INIT[16]
0 1 0 0 0 1 INIT[17] INIT[17]
0 1 0 0 1 0 INIT[18] INIT[18]
0 1 0 0 1 1 INIT[19] INIT[19]
0 1 0 1 0 0 INIT[20] INIT[20]
0 1 0 1 0 1 INIT[21] INIT[21]
0 1 0 1 1 0 INIT[22] INIT[22]
0 1 0 1 1 1 INIT[23] INIT[23]
0 1 1 0 0 0 INIT[24] INIT[24]
0 1 1 0 0 1 INIT[25] INIT[25]
0 1 1 0 1 0 INIT[26] INIT[26]
0 1 1 0 1 1 INIT[27] INIT[27]
0 1 1 1 0 0 INIT[28] INIT[28]
0 1 1 1 0 1 INIT[29] INIT[29]
0 1 1 1 1 0 INIT[30] INIT[30]
0 1 1 1 1 1 INIT[31] INIT[31]
1 0 0 0 0 0 INIT[0] INIT[32]
1 0 0 0 0 1 INIT[1] INIT[33]
1 0 0 0 1 0 INIT[2] INIT[34]
1 0 0 0 1 1 INIT[3] INIT[35]
1 0 0 1 0 0 INIT[4] INIT[36]
1 0 0 1 0 1 INIT[5] INIT[37]
1 0 0 1 1 0 INIT[6] INIT[38]
1 0 0 1 1 1 INIT[7] INIT[39]
1 0 1 0 0 0 INIT[8] INIT[40]
1 0 1 0 0 1 INIT[9] INIT[41]
1 0 1 0 1 0 INIT[10] INIT[42]
1 0 1 0 1 1 INIT[11] INIT[43]
1 0 1 1 0 0 INIT[12] INIT[44]
1 0 1 1 0 1 INIT[13] INIT[45]
1 0 1 1 1 0 INIT[14] INIT[46]
1 0 1 1 1 1 INIT[15] INIT[47]
1 1 0 0 0 0 INIT[16] INIT[48]
1 1 0 0 0 1 INIT[17] INIT[49]
1 1 0 0 1 0 INIT[18] INIT[50]
1 1 0 0 1 1 INIT[19] INIT[51]
1 1 0 1 0 0 INIT[20] INIT[52]
1 1 0 1 0 1 INIT[21] INIT[53]
1 1 0 1 1 0 INIT[22] INIT[54]
1 1 0 1 1 1 INIT[23] INIT[55]
1 1 1 0 0 0 INIT[24] INIT[56]
1 1 1 0 0 1 INIT[25] INIT[57]
1 1 1 0 1 0 INIT[26] INIT[58]
1 1 1 0 1 1 INIT[27] INIT[59]
1 1 1 1 0 0 INIT[28] INIT[60]
1 1 1 1 0 1 INIT[29] INIT[61]
1 1 1 1 1 0 INIT[30] INIT[62]
1 1 1 1 1 1 INIT[31] INIT[63]
INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

Port Descriptions

Port Direction Width Function
I0 Input 1 LUT input.
I1 Input 1 LUT input.
I2 Input 1 LUT input.
I3 Input 1 LUT input.
I4 Input 1 LUT input.
I5 Input 1 LUT input.
O5 Output 1 LUT output.
O6 Output 1 LUT output.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
INIT HEX Any 64-bit HEX value All zeroes Specifies the logical expression of this element.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration. 
Library UNISIM;
use UNISIM.vcomponents.all;

-- LUT6_2: 6-input  2 output Look-Up Table
--         7 Series
-- Xilinx HDL Language Template, version 2026.1

LUT6_2_inst : LUT6_2
generic map (
   INIT => X"0000000000000000") -- Specify LUT Contents
port map (
   O6 => O6,  -- 6/5-LUT output (1-bit)
   O5 => O5,  -- 5-LUT output (1-bit)
   I0 => I0,   -- LUT input (1-bit)
   I1 => I1,   -- LUT input (1-bit)
   I2 => I2,   -- LUT input (1-bit)
   I3 => I3,   -- LUT input (1-bit)
   I4 => I4,   -- LUT input (1-bit)
   I5 => I5    -- LUT input (1-bit)
);

-- End of LUT6_2_inst instantiation

Verilog Instantiation Template


// LUT6_2: 6-input, 2 output Look-Up Table
//         7 Series
// Xilinx HDL Language Template, version 2026.1

LUT6_2 #(
   .INIT(64'h0000000000000000) // Specify LUT Contents
) LUT6_2_inst (
   .O6(O6), // 1-bit LUT6 output
   .O5(O5), // 1-bit lower LUT5 output
   .I0(I0), // 1-bit LUT input
   .I1(I1), // 1-bit LUT input
   .I2(I2), // 1-bit LUT input
   .I3(I3), // 1-bit LUT input
   .I4(I4), // 1-bit LUT input
   .I5(I5)  // 1-bit LUT input (fast MUX select only available to O6 output)
);

// End of LUT6_2_inst instantiation

Related Information

  • 7 Series FPGAs Configurable Logic Block User Guide (UG474)