IOBUF_INTERMDISABLE - IOBUF_INTERMDISABLE - 2025.2 English - Primitive: Bi-Directional Single-ended Buffer with Input Termination Disable and Input Path Disable

Primitive: Bi-Directional Single-ended Buffer with Input Termination Disable and Input Path Disable

Introduction

The design element is a bidirectional single-ended I/O Buffer that connects the internal logic to an external bidirectional pin. This element include uncalibrated input termination (INTERM) disable and an input path disable as additional power saving features when the I/O is either is an unused state or used as an output for several clock cycles. You can only place this element in High Range (HR) banks in 7 series devices.

Port Descriptions

Port	Direction	Width	Function
O	Output	1	Buffer output representing the input path to the device.
IO	In/out	1	Bi-directional port connection. Connect directly to top-level port in the design.
I	Input	1	Buffer input representing the output path to the device.
IBUFDISABLE	Input	1	When USE_IBUFDISABLE is set to "TRUE", disables the input path through the buffer and forces to a logic high. If USE_IBUFDISABLE is set to "FALSE", this input is ignored and must be tied to ground. This feature is generally used to reduce power at times when the I/O is either idle or during sustained write (output) conditions.
INTERMDISABLE	Input	1	Disables input termination. This feature is generally used to reduce power at times when the I/O is either idle or during sustained write (output) conditions.
T	Input	1	Sets the I/O in a high impedance 3-state mode when the I/O is being used for a read (input) operation. The T pin also affects the IBUFDISABLE function when USE_IBUFDISABLE = "TRUE." The T pin also disables INTERM when in a write (output) mode.

Design Entry Method

Instantiation	Yes
Inference	No
IP catalog	Yes
Macro support	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
DRIVE	INTEGER	2, 4, 6, 8, 12, 16, 24	12	Selects output drive strength (mA) for the SelectIObuffers.
IBUF_LOW_PWR	STRING	"TRUE", "FALSE"	"TRUE"	Allows a trade off of lower power consumption vs. highest performance.
IOSTANDARD	STRING	See Data Sheet	"DEFAULT"	Assigns an I/O standard to the element.
SLEW	STRING	"SLOW", "FAST"	"SLOW"	Sets the output rise and fall time. See the Data Sheet for recommendations of the best setting for this attribute.
USE_IBUFDISABLE	STRING	"TRUE", "FALSE"	"TRUE"	Enables or disables the feature of IBUFDISABLE. Generally used when it is not desirable to have the T pin disable input path to allow a read during write operation.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- IOBUF_INTERMDISABLE: Single-ended Bi-directional Buffer with Input Termination
--                      and Input path enable/disable
--                      May only be placed in High Range (HR) Banks
--                      7 Series
-- Xilinx HDL Language Template, version 2025.2

IOBUF_INTERMDISABLE_inst : IOBUF_INTERMDISABLE
generic map (
   DRIVE => 12,
   IOSTANDARD => "DEFAULT", -- Specify the I/O standard
   IBUF_LOW_PWR => "TRUE", -- Low Power - "TRUE", High Performance = "FALSE"
   USE_IBUFDISABLE => "TRUE", -- Use IBUFDISABLE function "TRUE" or "FALSE"
   SLEW => "SLOW")
port map (
   O => O,     -- Buffer output
   IO => IO,   -- Buffer inout port (connect directly to top-level port)
   DCITERMDISABLE => DCITERMDISABLE, -- DCI Termination enable input
   I => I,     -- Buffer input
   IBUFDISABLE => IBUFDISABLE, -- Input disable input, high=disable
   INTERMDISABLE => INTERMDISABLE, -- Input termination disable input
   T => T      -- 3-state enable input, high=input, low=output
);

-- End of IOBUF_DCIEN_inst instantiation

Verilog Instantiation Template


// IOBUF_INTERMDISABLE: Single-ended Bi-directional Buffer with Input Termination
//                      and Input path enable/disable
//                      May only be placed in High Range (HR) Banks
//                      7 Series
// Xilinx HDL Language Template, version 2025.2

IOBUF_INTERMDISABLE #(
   .DRIVE(12), // Specify the output drive strength
   .IBUF_LOW_PWR("TRUE"),  // Low Power - "TRUE", High Performance = "FALSE"
   .IOSTANDARD("DEFAULT"), // Specify the I/O standard
   .SLEW("SLOW"),          // Specify the output slew rate
   .USE_IBUFDISABLE("TRUE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
) IOBUF_INTERMDISABLE_inst (
   .O(O),     // Buffer output
   .IO(IO),   // Buffer inout port (connect directly to top-level port)
   .I(I),     // Buffer input
   .IBUFDISABLE(IBUFDISABLE), // Input disable input, high=disable
   .INTERMDISABLE(INTERMDISABLE), // Input termination disable input
   .T(T)      // 3-state enable input, high=input, low=output
);

// End of IOBUF_INTERMDISABLE_inst instantiation

Related Information

7 Series FPGAs SelectIO Resources User Guide (UG471)

IOBUF_INTERMDISABLE - IOBUF_INTERMDISABLE - 2025.2 English - Primitive: Bi-Directional Single-ended Buffer with Input Termination Disable and Input Path Disable - UG953