IOBUFDS_DIFF_OUT_INTERMDISABLE - IOBUFDS_DIFF_OUT_INTERMDISABLE - 2026.1 English - Primitive: Differential Bidirectional Buffer with Complementary Outputs, Input Buffer Disable and On-die Input Termination Disable

Primitive: Differential Bidirectional Buffer with Complementary Outputs, Input Buffer Disable and On-die Input Termination Disable

PRIMITIVE_GROUP: I/O
PRIMITIVE_SUBGROUP: BIDIR_BUFFER

Introduction

The IOBUFDS_DIFF_OUT_INTERMDISABLE primitive is available in the HD I/O banks. The IOBUFDS_DIFF_OUT_INTERMDISABLE primitive has an INTERMDISABLE port that can be used to disable the optional on-die receiver termination feature. TM and TS must be connected to the same input (T) from the interconnect logic for this primitive to have the expected behavior that is specific to the architecture.

The USE_IBUFDISABLE attribute must be set to TRUE and SIM_DEVICE to the appropriate value for the IOBUFDS_DIFF_OUT_INTERMDISABLE primitive to have the expected behavior that is specific to the architecture. If the I/O is using the on-die receiver termination features, this primitive disables the termination legs whenever the INTERMDISABLE signal is asserted High and the output buffer is 3-stated. When the output buffer is 3-stated (T = High), any on-die receiver termination is controlled by INTERMDISABLE. When the output buffer is not 3-stated (T = Low), the input buffer and on-die receiver termination are disabled and the O output (to the internal logic) is forced to a logic-Low.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property.

Port Descriptions

Port	Direction	Width	Function
I	Input	1	Input of OBUF. Connect to the logic driving the output port.
IBUFDISABLE	Input	1	The IBUFDISABLE feature is not supported with this primitive in the UltraScale architecture. This port must be tied to logic '0'.
INTERMDISABLE	Input	1	Control to enable/disable on-chip input termination. This is generally used to reduce power in long periods of an idle state.
IO	Inout	1	Bidirectional diff_p port to be connected directly to top-level inout port.
IOB	Inout	1	Bidirectional diff_n port to be connected directly to top-level inout port.
O	Output	1	Output path of the buffer.
OB	Output	1	Output path of the buffer.
TM	Input	1	3-state enable input for the p-side or master side signifying whether the buffer acts as an input or output. This pin must be connected to the same signal as the TS input.
TS	Input	1	3-state enable input for the n-side or slave side signifying whether the buffer acts as an input or output. This pin must be connected to the same signal as the TM input.

Design Entry Method

Instantiation	Recommended
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
SIM_DEVICE	STRING			Set the device version for simulation functionality.
USE_IBUFDISABLE	STRING	"TRUE", "FALSE", "T_CONTROL"	"TRUE"	This attribute must be unspecified or set to "TRUE" if specified.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- IOBUFDS_DIFF_OUT_INTERMDISABLE:  Differential Global Clock Buffer with Differential Output
--                                  Input Termination and Input Path Disable
--                                  May only be placed in High Range (HR) Banks
--                                  7 Series
-- Xilinx HDL Language Template, version 2026.1

IOBUFDS_DIFF_OUT_INTERMDISABLE_inst : IOBUFDS_DIFF_OUT_INTERMDISABLE
generic map (
   DIFF_TERM => "FALSE", -- Differential Termination (TRUE/FALSE)
   IBUF_LOW_PWR => "TRUE", -- Low Power - TRUE, High Performance = FALSE
   IOSTANDARD => "BLVDS_25", -- Specify the I/O standard
   USE_IBUFDISABLE => "TRUE") -- Use IBUFDISABLE function, "TRUE" or "FALSE"
port map (
   O => O,     -- Buffer p-side output
   OB => OB,   -- Buffer n-side output
   IO => IO,   -- Diff_p inout (connect directly to top-level port)
   IOB => IOB, -- Diff_n inout (connect directly to top-level port)
   I => I,     -- Buffer input
   IBUFDISABLE => IBUFDISABLE, -- input disable input, high=disable
   INTERMDISABLE => INTERMDISABLE, -- Input termination disable input
   TM => TM,   -- 3-state enable input, high=input, low=output
   TS => TS    -- 3-state enable input, high=output, low=input
);

-- End of IOBUFDS_DIFF_OUT_INTERMDISABLE_inst instantiation

Verilog Instantiation Template


// IOBUFDS_DIFF_OUT_INTERMDISABLE: Differential Global Clock Buffer with Differential Output
//                                 Input Termination and Input Path Disable
//                                 May only be placed in High Range (HR) Banks
//                                 7 Series
// Xilinx HDL Language Template, version 2026.1

IOBUFDS_DIFF_OUT_INTERMDISABLE #(
   .DIFF_TERM("FALSE"),     // Differential Termination, "TRUE"/"FALSE"
   .IBUF_LOW_PWR("TRUE"),   // Low power="TRUE", Highest performance="FALSE"
   .IOSTANDARD("DEFAULT"),  // Specify the input I/O standard
   .USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
) IOBUFDS_DIFF_OUT_INTERMDISABLE_inst (
   .O(O),     // Buffer p-side output
   .OB(OB),   // Buffer n-side output
   .IO(IO),   // Diff_p inout (connect directly to top-level port)
   .IOB(IOB), // Diff_n inout (connect directly to top-level port)
   .I(I),     // Buffer input
   .INTERMDISABLE(INTERMDISABLE), //  Input termination disable input
   .IBUFDISABLE(IBUFDISABLE),     // Input disable input, high=disable
   .TM(TM),   // 3-state enable input, high=input, low=output
   .TS(TS)    // 3-state enable input, high=input, low=output
);

// End of IOBUFDS_DIFF_OUT_INTERMDISABLE_inst instantiation

Related Information

7 Series FPGAs SelectIO Resources User Guide (UG471)

IOBUFDS_DIFF_OUT_INTERMDISABLE - IOBUFDS_DIFF_OUT_INTERMDISABLE - 2026.1 English - Primitive: Differential Bidirectional Buffer with Complementary Outputs, Input Buffer Disable and On-die Input Termination Disable - UG953