IOBUFDS_DIFF_OUT - IOBUFDS_DIFF_OUT - 2026.1 English - Primitive: Differential Input/Output Buffer Primitive With Complementary Outputs for the Input Buffer

Primitive: Differential Input/Output Buffer Primitive With Complementary Outputs for the Input Buffer

PRIMITIVE_GROUP: I/O
PRIMITIVE_SUBGROUP: BIDIR_BUFFER

Introduction

The IOBUFDS_DIFF_OUT is a differential input/output buffer primitive with complementary outputs (O and OB). A logic-High on the T pin disables the output buffer. When the output buffer is 3-stated (T = High), the input buffer and any on-die receiver termination (uncalibrated or DCI) are ON. When the output buffer is not 3-stated (T = Low), any on-die receiver termination (uncalibrated or DCI) is disabled. TM and TS must be connected to the same input from the interconnect logic for this primitive to have the expected behavior that is specific to the architecture.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property.

Port Descriptions

Port	Direction	Width	Function
I	Input	1	Input of OBUF. Connect to the logic driving the output port.
IO	Inout	1	Bidirectional diff_p port to be connected directly to top-level inout port.
IOB	Inout	1	Bidirectional diff_n port to be connected directly to top-level inout port.
O	Output	1	Output path of the buffer.
OB	Output	1	Output path of the buffer.
TM	Input	1	3-state enable input for the p-side or master side signifying whether the buffer acts as an input or output. This pin must be connected to the same signal as the TS input.
TS	Input	1	3-state enable input for the n-side or slave side signifying whether the buffer acts as an input or output. This pin must be connected to the same signal as the TM input.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- IOBUFDS_DIFF_OUT: Differential Bi-directional Buffer with Diffirential Output
--                   7 Series
-- Xilinx HDL Language Template, version 2026.1

IOBUFDS_DIFF_OUT_inst : IOBUFDS_DIFF_OUT
generic map (
   DIFF_TERM => FALSE, -- Differential Termination (TRUE/FALSE)
   IBUF_LOW_PWR => TRUE, -- Low Power - TRUE, High Performance = FALSE
   IOSTANDARD => "BLVDS_25") -- Specify the I/O standard
port map (
   O => O,     -- Buffer p-side output
   OB => OB,   -- Buffer n-side output
   IO => IO,   -- Diff_p inout (connect directly to top-level port)
   IOB => IOB, -- Diff_n inout (connect directly to top-level port)
   I => I,     -- Buffer input
   TM => TM,   -- 3-state enable input, high=input, low=output
   TS => TS    -- 3-state enable input, high=input, low=output
);

-- End of IOBUFDS_DIFF_OUT_inst instantiation

Verilog Instantiation Template


// IOBUFDS_DIFF_OUT: Differential Bi-directional Buffer with Differential Output
//                   7 Series
// Xilinx HDL Language Template, version 2026.1

IOBUFDS_DIFF_OUT #(
   .DIFF_TERM("FALSE"),    // Differential Termination ("TRUE"/"FALSE")
   .IBUF_LOW_PWR("TRUE"),  // Low Power - "TRUE", High Performance = "FALSE"
   .IOSTANDARD("BLVDS_25") // Specify the I/O standard
) IOBUFDS_DIFF_OUT_inst (
   .O(O),     // Buffer p-side output
   .OB(OB),   // Buffer n-side output
   .IO(IO),   // Diff_p inout (connect directly to top-level port)
   .IOB(IOB), // Diff_n inout (connect directly to top-level port)
   .I(I),     // Buffer input
   .TM(TM),   // 3-state enable input, high=input, low=output
   .TS(TS)    // 3-state enable input, high=input, low=output
);

// End of IOBUFDS_DIFF_OUT_inst instantiation

Related Information

7 Series FPGAs SelectIO Resources User Guide (UG471)