IDELAYCTRL - IDELAYCTRL - 2025.2 English - Primitive: IDELAYE2/ODELAYE2 Tap Delay Value Control

Primitive: IDELAYE2/ODELAYE2 Tap Delay Value Control

Introduction

When using IDELAYE2 or ODELAYE2, you must instantiate at least one of these design elements. The IDELAYCTRL module provides a reference clock input allowing internal circuitry to derive a voltage bias, independent of PVT (process, voltage, and temperature) variations, defining precise delay tap values for the associated IDELAYE2 and ODELAYE2 components. When instantiating this component to distinguish which IDELAYCTRL is associated with IDELAYE2 and ODELAYE2, use the IODELAY_GROUP attribute.

Port Descriptions

Port	Direction	Width	Function
RDY	Output	1	The ready (RDY) signal indicates when the IDELAYE2 and ODELAYE2 modules in the specific region are calibrated. If REFCLK is held High or Low for one clock period or more, the RDY signal deasserts. If RDY deasserts Low, you must reset the IDELAYCTRL module. If not needed, RDY can be unconnected/ignored.
REFCLK	Input	1	Time reference to IDELAYCTRL to calibrate all IDELAYE2 and ODELAYE2 modules in the same region. REFCLK can be supplied directly from a user-supplied source or the MMCME2/PLLE2 and must be routed on a global clock buffer.
RST	Input	1	Active-High asynchronous reset. To ensure proper IDELAYE2 and ODELAYE2 operation, IDELAYCTRL must be reset after configuration and the REFCLK signal is stable. A reset pulse width Tidelayctrl_rpw is required.

RST (Module reset) Resets the IDELAYCTRL circuitry. The RST signal is an active-High asynchronous reset. To reset the IDELAYCTRL, assert it High for at least 50 ns.

REFCLK (Reference Clock) Provides a voltage bias, independent of process, voltage, and temperature variations, to the tap-delay lines in the IOBs. The frequency of REFCLK must be 200 MHz to guarantee the tap-delay value specified in the applicable data sheet.

RDY (Ready Output) Indicates the validity of the reference clock input, REFCLK. When REFCLK disappears (that is, REFCLK is held High or Low for one clock period or more), the RDY signal deasserts.

Design Entry Method

Instantiation	Yes
Inference	No
IP catalog	Yes
Macro support	No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control
--             7 Series
-- Xilinx HDL Language Template, version 2025.2

IDELAYCTRL_inst : IDELAYCTRL
port map (
   RDY => RDY,       -- 1-bit output: Ready output
   REFCLK => REFCLK, -- 1-bit input: Reference clock input
   RST => RST        -- 1-bit input: Active high reset input
);

-- End of IDELAYCTRL_inst instantiation

Verilog Instantiation Template


// IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control
//             7 Series
// Xilinx HDL Language Template, version 2025.2

(* IODELAY_GROUP = <iodelay_group_name> *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL

IDELAYCTRL IDELAYCTRL_inst (
   .RDY(RDY),       // 1-bit output: Ready output
   .REFCLK(REFCLK), // 1-bit input: Reference clock input
   .RST(RST)        // 1-bit input: Active high reset input
);

// End of IDELAYCTRL_inst instantiation

Related Information

7 Series FPGAs SelectIO Resources User Guide (UG471)