IBUF_IBUFDISABLE - IBUF_IBUFDISABLE - 2026.1 English - Primitive: Input Buffer With Input Buffer Disable

Primitive: Input Buffer With Input Buffer Disable

PRIMITIVE_GROUP: I/O
PRIMITIVE_SUBGROUP: INPUT_BUFFER

Introduction

The IBUF_IBUFDISABLE primitive is an input buffer with a disable port that can be used as an additional power saving feature for periods when the input is not used.

The IBUF_IBUFDISABLE primitive can disable the input buffer and force the O output to the internal logic to a logic-Low when the IBUFDISABLE signal is asserted High. The USE_IBUFDISABLE attribute must be set to TRUE and SIM_DEVICE to the appropriate value for this primitive to have the expected behavior specific to the architecture. This feature can be used to reduce power at times when the I/O is idle. Input buffers that use the VREF power rail (such as SSTL and HSTL) benefit the most from the IBUFDISABLE being set to TRUE because they tend to have higher static power consumption than the non-VREF standards such as LVCMOS and LVTTL.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property.

Port Descriptions

Port	Direction	Width	Function
I	Input	1	Input port connection. Connect directly to top-level port in the design.
IBUFDISABLE	Input	1	Disables input path through the buffer and forces to a logic Low. This feature is generally used to reduce power at times when the I/O is idle for a period of time.
O	Output	1	Buffer output representing the input path to the device.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
SIM_DEVICE	STRING			Set the device version for simulation functionality.
USE_IBUFDISABLE	STRING	"TRUE", "FALSE", "T_CONTROL"	"TRUE"	Set this attribute to "TRUE" to enable the IBUFDISABLE pin.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- IBUF_IBUFDISABLE: Single-ended Input Buffer with Disable
--                   7 Series
-- Xilinx HDL Language Template, version 2026.1

IBUF_IBUFDISABLE_inst : IBUF_IBUFDISABLE
generic map (
   IBUF_LOW_PWR => "TRUE", -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
   IOSTANDARD => "DEFAULT", -- Specify the input I/O standard
   USE_IBUFDISABLE => "TRUE") -- Set to "TRUE" to enable IBUFDISABLE feature
port map (
   O => O,     -- Buffer output
   I => I,     -- Buffer input (connect directly to top-level port)
   IBUFDISABLE => IBUFDISABLE -- Buffer disable input, low=disable
);

-- End of IBUF_IBUFDISABLE_inst instantiation

Verilog Instantiation Template


// IBUF_IBUFDISABLE: Single-ended Input Buffer with Disable
//                   7 Series
// Xilinx HDL Language Template, version 2026.1

IBUF_IBUFDISABLE #(
   .IBUF_LOW_PWR("TRUE"),   // Low power ("TRUE") vs. performance ("FALSE") for referenced I/O standards
   .IOSTANDARD("DEFAULT"),  // Specify the input I/O standard
   .USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
) IBUF_IBUFDISABLE_inst (
   .O(O),                    // Buffer output
   .I(I),                    // Buffer input (connect directly to top-level port)
   .IBUFDISABLE(IBUFDISABLE) // Buffer disable input, high=disable
);

// End of IBUF_IBUFDISABLE_inst instantiation

IBUF_IBUFDISABLE - IBUF_IBUFDISABLE - 2026.1 English - Primitive: Input Buffer With Input Buffer Disable - UG953