IBUFDS_GTE2 - IBUFDS_GTE2 - 2026.1 English - Primitive: Gigabit Transceiver Buffer

Primitive: Gigabit Transceiver Buffer

PRIMITIVE_GROUP: ADVANCED
PRIMITIVE_SUBGROUP: GT

Introduction

IBUFDS_GTE2 is the gigabit transceiver input pad buffer component in 7 series devices. The REFCLK signal must route to the dedicated reference clock input pins on the serial transceiver, and you must instantiate the IBUFDS_GTE2 primitive in your design. For more information on PCB layout requirements, including reference clock requirements, see the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476).

Port Descriptions

Port	Direction	Width	Function
CEB	Input	1	Refer to Transceiver User Guide.
I	Input	1	Refer to Transceiver User Guide.
IB	Input	1	Refer to Transceiver User Guide.
O	Output	1	Refer to Transceiver User Guide.
ODIV2	Output	1	Refer to Transceiver User Guide.

Design Entry Method

Instantiation	Yes
Inference	No
IP catalog	Recommended
Macro support	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
CLKRCV_TRST	Boolean	TRUE	TRUE	Refer to Transceiver User Guide.
CLKCM_CFG	Boolean	TRUE	TRUE	Refer to Transceiver User Guide.
CLKSWING_CFG[1:0]	Boolean	2'b11	2'b11	Refer to Transceiver User Guide.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- IBUFDS_GTE2: Gigabit Transceiver Buffer
--              7 Series
-- Xilinx HDL Language Template, version 2026.1

IBUFDS_GTE2_inst : IBUFDS_GTE2
generic map (
   CLKCM_CFG => TRUE,    -- Refer to Transceiver User Guide
   CLKRCV_TRST => TRUE,  -- Refer to Transceiver User Guide
   CLKSWING_CFG => '11'  -- Refer to Transceiver User Guide
)
port map (
   O => O,         -- 1-bit output: Refer to Transceiver User Guide
   ODIV2 => ODIV2, -- 1-bit output: Refer to Transceiver User Guide
   CEB => CEB,     -- 1-bit input: Refer to Transceiver User Guide
   I => I,         -- 1-bit input: Refer to Transceiver User Guide
   IB => IB        -- 1-bit input: Refer to Transceiver User Guide
);

-- End of IBUFDS_GTE2_inst instantiation

Verilog Instantiation Template


// IBUFDS_GTE2: Gigabit Transceiver Buffer
//              7 Series
// Xilinx HDL Language Template, version 2026.1

IBUFDS_GTE2 #(
   .CLKCM_CFG("TRUE"),   // Refer to Transceiver User Guide
   .CLKRCV_TRST("TRUE"), // Refer to Transceiver User Guide
   .CLKSWING_CFG(2'b11)  // Refer to Transceiver User Guide
)
IBUFDS_GTE2_inst (
   .O(O),         // 1-bit output: Refer to Transceiver User Guide
   .ODIV2(ODIV2), // 1-bit output: Refer to Transceiver User Guide
   .CEB(CEB),     // 1-bit input: Refer to Transceiver User Guide
   .I(I),         // 1-bit input: Refer to Transceiver User Guide
   .IB(IB)        // 1-bit input: Refer to Transceiver User Guide
);

// End of IBUFDS_GTE2_inst instantiation

Related Information

7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
7 Series FPGAs SelectIO Resources User Guide (UG471)

IBUFDS_GTE2 - IBUFDS_GTE2 - 2026.1 English - Primitive: Gigabit Transceiver Buffer - UG953