IBUFDS - IBUFDS - 2026.1 English - Primitive: Differential Input Buffer - UG953

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2026-06-23
Version
2026.1 English

Primitive: Differential Input Buffer

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: INPUT_BUFFER
Page-1 Graphic ID: SW & IP X10662 X10662-061219 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 I I Sheet.13 O O Sheet.14 Sheet.15 Sheet.16 Sheet.17 IB IB Sheet.18 Sheet.19 Sheet.20 Sheet.21 Inputs from Device Pads Inputs fromDevice Pads Sheet.22 IBUFDS IBUFDS

Introduction

The usage and rules corresponding to the differential primitives are similar to the single-ended SelectIO primitives. Differential SelectIO primitives have two pins to and from the device pads to show the P and N channel pins in a differential pair. N channel pins have a B suffix.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property.

Logic Table

Inputs Outputs
I IB O
0 0 No Change
0 1 0
1 0 1
1 1 No Change

Port Descriptions

Port Direction Width Function
I Input 1 Diff_p Buffer Input. Connect to top-level p-side input port.
IB Input 1 Diff_n Buffer Input. Connect to top-level n-side input port.
O Output 1 Buffer output

Design Entry Method

Instantiation Recommended
Inference No
IP and IP Integrator Catalog No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- IBUFDS: Differential Input Buffer
--         7 Series
-- Xilinx HDL Language Template, version 2026.1

IBUFDS_inst : IBUFDS
generic map (
   DIFF_TERM => FALSE, -- Differential Termination
   IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
   IOSTANDARD => "DEFAULT")
port map (
   O => O,  -- Buffer output
   I => I,  -- Diff_p buffer input (connect directly to top-level port)
   IB => IB -- Diff_n buffer input (connect directly to top-level port)
);

-- End of IBUFDS_inst instantiation

Verilog Instantiation Template


// IBUFDS: Differential Input Buffer
//         7 Series
// Xilinx HDL Language Template, version 2026.1

IBUFDS #(
   .DIFF_TERM("FALSE"),       // Differential Termination
   .IBUF_LOW_PWR("TRUE"),     // Low power="TRUE", Highest performance="FALSE"
   .IOSTANDARD("DEFAULT")     // Specify the input I/O standard
) IBUFDS_inst (
   .O(O),  // Buffer output
   .I(I),  // Diff_p buffer input (connect directly to top-level port)
   .IB(IB) // Diff_n buffer input (connect directly to top-level port)
);

// End of IBUFDS_inst instantiation

Related Information

  • 7 Series FPGAs SelectIO Resources User Guide (UG471)