Primitive: Input Buffer
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: INPUT_BUFFER
Introduction
Single-ended signals used as simple inputs must use an input buffer (IBUF).
I/O attributes that do not impact the logic function of the component, such as IOSTANDARD and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| I | Input | 1 | Buffer input connected to a top-level input port. |
| O | Output | 1 | Buffer output connected to internal device circuitry. |
Design Entry Method
| Instantiation | Yes |
| Inference | Recommended |
| IP and IP Integrator Catalog | No |
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IBUF: Single-ended Input Buffer
-- 7 Series
-- Xilinx HDL Language Template, version 2026.1
IBUF_inst : IBUF
generic map (
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => O, -- Buffer output
I => I -- Buffer input (connect directly to top-level port)
);
-- End of IBUF_inst instantiation
Verilog Instantiation Template
// IBUF: Single-ended Input Buffer
// 7 Series
// Xilinx HDL Language Template, version 2026.1
IBUF #(
.IBUF_LOW_PWR("TRUE"), // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
) IBUF_inst (
.O(O), // Buffer output
.I(I) // Buffer input (connect directly to top-level port)
);
// End of IBUF_inst instantiation