This design element is a single D-type flip-flop with clock enable and asynchronous preset.
When clock enable (CE) is High and asynchronous preset (PRE) is not asserted, the data on the data input (D) of
this design element is transferred to the corresponding data output (Q) during the
clock (C) transition.
When PRE is asserted, it overrides all other inputs and presets the data output
(Q) High.
When CE is Low, clock transitions are ignored.
This flip-flop is asynchronously initialized when power is applied.
When global set/reset (GSR) is active upon power-up or when GSR is
asserted,
the value of the INIT attribute is placed on the register's output.
Logic Table
Inputs
Outputs
PRE
CE
D
C
Q
1
X
X
X
1
0
0
X
X
No Change
0
1
D
↑
D
Port Descriptions
Port
Direction
Width
Function
C
Input
1
Clock input. Polarity is determined by the IS_C_INVERTED attribute.
CE
Input
1
Active-High register clock enable.
D
Input
1
Data input
PRE
Input
1
Asynchronous preset. Polarity is determined by the IS_PRE_INVERTED attribute.
Q
Output
1
Data output.
Design Entry Method
Instantiation
Yes
Inference
Recommended
IP and IP Integrator Catalog
No
Available Attributes
Attribute
Type
Allowed Values
Default
Description
INIT
BINARY
1'b1, 1'b0
1'b1
Sets the initial value of Q output after configuration or when GSR is asserted.
Programmable Inversion Attributes: Specifies whether or not to use the optional inversion on specific pins for this component to change the
active polarity of the pin function. When set to 1 on a clock pin (C), it creates a negative edge register.
When set to 1 on other pins, it changes the function to behave active-Low rather than active-High.
If an external inverter is specified on one of these associated pins, the Vivado Design Suite will automatically
set this attribute during the opt_design stage so that additional logic is not necessary for changing the
input polarity.
IS_C_INVERTED
BINARY
1'b0 to 1'b1
1'b0
Specifies whether or not to use the optional inversion for the C pin of this component.
IS_D_INVERTED
BINARY
1'b0 to 1'b1
1'b0
Specifies whether or not to use the optional inversion for the D pin of this component. Must be set to 0 unless used as an I/O register.
IS_PRE_INVERTED
BINARY
1'b0 to 1'b1
1'b0
Specifies whether or not to use the optional inversion for the PRE pin of this component.
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- FDPE: Single Data Rate D Flip-Flop with Asynchronous Preset and
-- Clock Enable (posedge clk).
-- 7 Series
-- Xilinx HDL Language Template, version 2026.1
FDPE_inst : FDPE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => Q, -- Data output
C => C, -- Clock input
CE => CE, -- Clock enable input
PRE => PRE, -- Asynchronous preset input
D => D -- Data input
);
-- End of FDPE_inst instantiation
Verilog Instantiation Template
// FDPE: Single Data Rate D Flip-Flop with Asynchronous Preset and
// Clock Enable (posedge clk).
// 7 Series
// Xilinx HDL Language Template, version 2026.1
FDPE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDPE_inst (
.Q(Q), // 1-bit Data output
.C(C), // 1-bit Clock input
.CE(CE), // 1-bit Clock enable input
.PRE(PRE), // 1-bit Asynchronous preset input
.D(D) // 1-bit Data input
);
// End of FDPE_inst instantiation
Related Information
7
Series FPGAs Configurable Logic Block User Guide (UG474)