About Design Elements
This section describes the design elements that can be used with 7 series FPGAs and Zynq™ 7000 SoC devices. The design elements are organized alphabetically.
The following information is provided for each design element, where applicable:
- Name, description, primitive group, and primitive subgroup
- Schematic symbol
- Introduction
- Logic table (if any)
- Port descriptions
- Design Entry Method
- Available attributes (if any)
- Example instantiation templates
- Links to related information
Instantiation Templates
Instantiation templates for library elements are also available in AMD Vivado™ , as well as in a downloadable ZIP file. Because PDF includes headers and footers if you copy text that spans pages, copy templates from Vivado or the downloaded ZIP file whenever possible.
Instantiation templates for this document can be found on the Web in 7_Series_Library_Guide_2026.1_HDL_Templates.zip .