Primitive: Regional Clock Buffer for I/O and Logic Resources
within a Clock Region
Introduction
BUFR is a regional clock buffer that drives clock signals to a dedicated clock net
within a clock region, independent from the global clock tree. Each BUFR drives the regional clock
nets in the region in which it is located. Unlike BUFIO components, BUFR components can drive the
I/O logic and logic resources (CLB, block RAM, etc.) in the existing clock region. An IBUF, BUFMRCE,
MMCM, or local interconnect drives them, and they generate divided clock outputs from the clock
input. The divide value is an integer between one and eight. BUFR components are ideal for
source-synchronous applications requiring clock domain crossing or serial-to-parallel conversion.
There are two BUFR components in a typical clock region (two regional clock networks). The BUFMRCE
can drive multiple BUFR components in adjacent clock regions to further extend clocking capability
if local clocking is needed in multiple clock regions. For more details, refer to BUFMRCE.
Port Descriptions
| Port |
Direction |
Width |
Function |
| CE |
Input |
1 |
Clock enable port. When asserted low, this port disables the output clock.
When asserted high, the clock propagates to the output port (O). This pin cannot be used in "BYPASS"
mode. Connect to vcc when BUFR_DIVIDE is set to "BYPASS" or not used. |
| CLR |
Input |
1 |
Counter asynchronous clear for divided clock output. When asserted high, this
port resets the counter used to produce the divided clock output and the output is asserted low.
This pin cannot be used in "BYPASS" mode. Connect to gnd when BUFR_DIVIDE is set to "BYPASS" or not
used. |
| I |
Input |
1 |
Clock input port. This port is the clock source port for BUFR. An IBUF,
BUFMRCE, MMCM, or local interconnect can drive it. |
| O |
Output |
1 |
Clock output port. This port drives the clock tracks in the
clock region of the BUFR. It connects to FPGA clocked components. |
Design Entry Method
| Instantiation |
Yes |
| Inference |
No |
| IP catalog |
Yes |
| Macro support |
No |
Available Attributes
| Attribute |
Type |
Allowed_Values |
Default |
Description |
| BUFR_DIVIDE |
STRING |
"BYPASS", "1", "2", "3", "4", "5", "6", "7", "8" |
"BYPASS" |
Specifies whether the output clock is a divided version of
the input clock. |
| SIM_DEVICE |
STRING |
"7SERIES" |
"7SERIES" |
For correct simulation behavior, this attribute must be set to "7SERIES" when
targeting a 7 series device. |
VHDL
Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFR: Regional Clock Buffer for I/O and Logic Resources within a Clock Region
-- 7 Series
-- Xilinx HDL Language Template, version 2025.2
BUFR_inst : BUFR
generic map (
BUFR_DIVIDE => "BYPASS", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => O, -- 1-bit output: Clock output port
CE => CE, -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => CLR, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => I -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
-- End of BUFR_inst instantiation
Verilog
Instantiation Template
// BUFR: Regional Clock Buffer for I/O and Logic Resources within a Clock Region
// 7 Series
// Xilinx HDL Language Template, version 2025.2
BUFR #(
.BUFR_DIVIDE("BYPASS"), // Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
.SIM_DEVICE("7SERIES") // Must be set to "7SERIES"
)
BUFR_inst (
.O(O), // 1-bit output: Clock output port
.CE(CE), // 1-bit input: Active high, clock enable (Divided modes only)
.CLR(CLR), // 1-bit input: Active high, asynchronous clear (Divided modes only)
.I(I) // 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
// End of BUFR_inst instantiation