Primitive: Multi-Region Clock Buffer
Introduction
The BUFMR is a multi-region clock-in/clock-out buffer. The BUFMR replaces the multi-region/bank support of the BUFR and BUFIO available in prior Virtex 7 architectures. Each bank contains two BUFMRs, and one specific MRCC in the same bank can drive each buffer. The BUFMRs drive the BUFIOs and/or BUFRs in the same region/banks and in the region above and below via the I/O clocking backbone. Do not use a BUFMR when driving BUFRs using clock dividers (not in bypass), but instead use a BUFMRCE component.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| I | Input | 1 | BUFMR clock input pin. Connect to an IBUF input that in turn is directly connected to a MRCC I/O port. |
| O | Output | 1 | BUFMR clock output pin. Connect to BUFIOs and/or BUFRs to be driven in adjacent regions. |
Design Entry Method
| Instantiation | Yes |
| Inference | No |
| IP catalog | No |
| Macro support | No |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFMR: Multi-Region Clock Buffer
-- 7 Series
-- Xilinx HDL Language Template, version 2025.2
BUFMR_inst : BUFMR
port map (
O => O, -- 1-bit output: Clock output (connect to BUFIOs/BUFRs)
I => I -- 1-bit input: Clock input (Connect to IBUF)
);
-- End of BUFMR_inst instantiation
Verilog Instantiation Template
// BUFMR: Multi-Region Clock Buffer
// 7 Series
// Xilinx HDL Language Template, version 2025.2
BUFMR BUFMR_inst (
.O(O), // 1-bit output: Clock output (connect to BUFIOs/BUFRs)
.I(I) // 1-bit input: Clock input (Connect to IBUF)
);
// End of BUFMR_inst instantiation
Related Information
- 7 Series FPGAs Clocking Resources User Guide (UG472)