This design element is a general clock buffer with a single gated
input. When clock enable (CE) is Low (inactive), its O output is 1.
When CE is High, the I input is transferred to the O
output.
Logic Table
Inputs
Outputs
I
CE
O
X
0
1
I
1
I
Port Descriptions
Port
Direction
Width
Function
CE
Input
1
Clock buffer active-High enable.
I
Input
1
Clock input.
O
Output
1
Clock output.
Design Entry Method
Instantiation
Yes
Inference
No
IP and IP Integrator Catalog
No
Available Attributes
Attribute
Type
Allowed Values
Default
Description
SIM_DEVICE
STRING
"ULTRASCALE"
Set the device version
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFGCE_1: Global Clock Buffer with Clock Enable and Output State 1
-- 7 Series
-- Xilinx HDL Language Template, version 2026.1
BUFGCE_1_inst : BUFGCE_1
port map (
O => O, -- 1-bit output: Clock output
CE => CE, -- 1-bit input: Clock enable input for I0
I => I -- 1-bit input: Primary clock
);
-- End of BUFGCE_1_inst instantiation
Verilog Instantiation Template
// BUFGCE_1: Global Clock Buffer with Clock Enable and Output State 1
// 7 Series
// Xilinx HDL Language Template, version 2026.1
BUFGCE_1 BUFGCE_1_inst (
.O(O), // 1-bit output: Clock output
.CE(CE), // 1-bit input: Clock enable input for I0
.I(I) // 1-bit input: Primary clock
);
// End of BUFGCE_1_inst instantiation
Related Information
7
Series FPGAs Clocking Resources User Guide (UG472)