This design element is a general clock buffer with a single gated
input. When clock enable (CE) is Low (inactive), its O output is 0.
When CE is High, the I input is transferred to the O
output.
Logic Table
Inputs
Outputs
I
CE
O
X
0
0
I
1
I
Port Descriptions
Port
Direction
Width
Function
CE
Input
1
Clock buffer active-High enable.
I
Input
1
Buffer input.
O
Output
1
Buffer output.
Design Entry Method
Instantiation
Recommended
Inference
Yes
IP and IP Integrator Catalog
No
Available Attributes
Attribute
Type
Allowed Values
Default
Description
CE_TYPE
STRING
"SYNC", "ASYNC", "HARDSYNC"
"SYNC"
Specifies whether the enable should be synchronous
(glitch-free) or asynchronous (no input clock switching
necessary). Versal devices have a an optional hardened
synchronizer circuit that can be enabled by using the
HARDSYNC setting.
IS_CE_INVERTED
BINARY
1'b0 to 1'b1
1'b0
Specifies use of the programmable inversion on the CE pin.
IS_I_INVERTED
BINARY
1'b0 to 1'b1
1'b0
Specifies use of the programmable inversion on the I pin.
SIM_DEVICE
STRING
Set the device version
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFGCE: Global Clock Buffer with Clock Enable
-- 7 Series
-- Xilinx HDL Language Template, version 2026.1
BUFGCE_inst : BUFGCE
port map (
O => O, -- 1-bit output: Clock output
CE => CE, -- 1-bit input: Clock enable input for I0
I => I -- 1-bit input: Primary clock
);
-- End of BUFGCE_inst instantiation
Verilog Instantiation Template
// BUFGCE: Global Clock Buffer with Clock Enable
// 7 Series
// Xilinx HDL Language Template, version 2026.1
BUFGCE BUFGCE_inst (
.O(O), // 1-bit output: Clock output
.CE(CE), // 1-bit input: Clock enable input for I0
.I(I) // 1-bit input: Primary clock
);
// End of BUFGCE_inst instantiation
Related Information
7
Series FPGAs Clocking Resources User Guide (UG472)