Review the Logic Level and Routes Distribution Tables - 2024.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)
Document ID
UG949
Release Date
2024-12-18
Version
2024.2 English

Longer paths are usually optimized first by the placer to meet timing, which potentially degrades the placement quality of shorter paths. Eliminating the longer paths can improve the overall timing QoR if completed before placement. To review longer paths, use the report_design_analysis command to generate the following tables:

Logic Level Distribution Table
Shows the distribution of logic levels in the top 1000 paths by default.
Routes Distribution Table
Shows the distribution of the number of routes within a timing path that must be routed through normal interconnect. For example, this table excludes nets that use intra-site and other dedicated routing resources.
Note: When paths show a disproportionate number of logic levels in relation to their logic delay, these paths have a lower number of routes than logic levels and typically contain MUXF or carry chain elements.
The following figure shows an example of the Logic Level Distribution for a design where the worst 5000 paths include difficult paths with 17 logic levels while the clock period is 7.5 ns. Run the following command to obtain this report:
report_design_analysis -logic_level_distribution -logic_level_dist_paths 5000 -name design_analysis_prePlace
Figure 1. Report Design Analysis Timing Path Characteristics Pre-Place

For logic levels above 10, you can use the -min_level and -max_level options to provide more distribution information for paths between the min and max level you identify. For example:

report_design_analysis -logic_level_distribution -min_level 16 -max_level 20 
-logic_level_dist_paths 5000 -name design_analysis_1

Run the following command to generate the timing report of the longest paths:

report_timing -name longPaths -of_objects [get_timing_paths -setup -to [get_clocks 
cpuClk_5] -max_paths 5000 -filter {LOGIC_LEVELS>=16 && LOGIC_LEVELS<=20}]

Based on what you find, you can improve the netlist by changing the RTL or using different synthesis options, or you can modify the timing and physical constraints.