Placement (place_design) - Placement (place_design) - 2026.1 English - UG949

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2026-06-23
Version
2026.1 English

The Vivado Design Suite placer engine positions cells from the netlist onto specific sites in the target AMD device.