Identifying the Clocks Related to Each Port - 2025.1 English - UG949

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2025-5-29
Version
2025.1 English

Before defining the I/O delay constraint, you must identify which clocks are related to each port. You can identify the clocks using the methods described in the following sections.