Step 1: Timing Analysis in System Generator - 2020.2 English

Vivado Design Suite Tutorial: Model-Based DSP Design Using System Generator (UG948)

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2020.2 English
  1. Invoke System Generator.
    • On Windows systems select Start > All Programs > Xilinx Design Tools > Vivado 2020.x > System Generator > System Generator 2020.x.
    • On Linux systems, type sysgen at the command prompt.
  2. Navigate to the Lab3 folder: cd C:\SysGen-Tutorial\Lab3.

    You can view the directory contents in the MATLAB® Current Folder browser, or type ls at the command line prompt.

  3. Open the Lab3 design using one of the following:
    • At the MATLAB command prompt, type open Lab3.slx
    • Double-click Lab3.slx in the Current Folder browser.

    The Lab3 design opens, as shown in the following figure.

  4. From your Simulink project worksheet, select Simulation > Run or click the Run simulation button to simulate the design.
  5. Double-click the System Generator token to open the Properties Editor.
  6. Select the Clocking tab.
  7. From the Perform analysis menu, select Post Synthesis and from Analyzer type menu select Timing as shown in the following figure.

  8. In the System Generator token dialog box, click Generate.

    When you generate, the following occurs:

    1. System Generator generates the required files for the selected compilation target. For timing analysis System Generator invokes the Vivado® Design Suite in the background for the design project, and passes design timing constraints to the Vivado Design Suite.
    2. Depending on your selection for Perform Analysis (Post Synthesis or Post Implementation), the design runs in the Vivado Design Suite through synthesis or through implementation.
    3. After the Vivado tools run is completed, timing paths information is collected and saved in a specific file format from the Vivado timing database.
    4. System Generator processes the timing information and displays a Timing Analyzer table with timing paths information as shown in the following figure.

  9. In the timing analyzer table:
    • Paths with lowest slack values display, with the worst Slack at the top and increasing slack below
    • Paths with timing violations have a negative slack and display in red.
  10. Cross probe from the Timing Analyzer table to the Simulink model by clicking any path in the Timing Analyzer table, which highlights the corresponding System Generator blocks in the model. This allows you to troubleshoot timing violations by analyzing the path on which they occur.
  11. When you cross probe, you see the corresponding path as shown in the following figure.
  12. Blocks with timing violations are highlighted in red.

  13. Double-click the second path in the Timing Analyzer table and cross-probe, the corresponding highlighted path in green which indicates no timing violation.