Part 2: Including a Vitis HLS Package in a System Generator Design - 2020.2 English

Vivado Design Suite Tutorial: Model-Based DSP Design Using System Generator (UG948)

Document ID
UG948
Release Date
2020-12-11
Version
2020.2 English
  1. Launch System Generator and open the Lab2_3.slx file in the Lab2/C_code folder. This should open the model as shown in the following figure.

  2. Add a Vitis HLS:
    1. Right-click anywhere on the canvas workspace.
    2. Select Xilinx BlockAdd.
    3. Type Vitis HLS in the Add block dialog box.
    4. Select Vitis HLS as shown in the following figure.


  3. Double-click the Vivado HLS block to open the Properties Editor.
  4. Use the Browse button to select the solution created by Vivado HLS in Step 1, at C:/SysGen_Tutorial/Lab2/C_code/hls_project/solution1, as shown in the following figure.
  5. Click OK to import the Vivado HLS IP.

  6. Connect the input and output ports of the block as shown in the following figure.

  7. Navigate into the Noisy Image sub-system and double-click the Image From File block xilinx_logo.png to open the Block Parameters dialog box.
  8. Use the Browse button to ensure the file name correctly point to the file xilinx_logo.jpg as shown in the following figure.

  9. Click OK to exit the Block Parameters dialog box.
  10. Use the Up to Parent toolbar button to return to the top level.
  11. Save the design.
  12. Simulate the design and verify the image is filtered, as shown in the following figures.