Structural Netlists for Simulation - Structural Netlists for Simulation - 2026.1 English - UG939

Vivado Design Suite Tutorial: Designing with IP (UG939)
Document ID
UG939
Release Date
2026-07-15
Version
2026.1 English

Depending on which Simulator Language you select during the Manage IP project creation, the results of the get_files commands above differ.

With some IP, you can not be able to perform behavioral simulation if you did not specify support for a Mixed simulator. Instead, you can have selected Verilog or VHDL.

You need to run simulations using a structural netlist, which the Vivado Design Suite produces automatically when a synthesized design checkpoint is available.

If the IP can deliver behavioral simulation files based upon your selected simulator language. When generating the output products you see Behavioral Simulation listed as an output product.

However, if the IP does not deliver simulation files for the selected simulator language, you see Structural Simulation as shown in the following figure.

Tip: The system always creates structural simulation output products for both Verilog and VHDL when it produces a synthesized design checkpoint. Querying the simulation files with get_files varies depending on whether behavioral simulation was possible with the selected simulator language setting.