Step 7: Run Implementation - Step 7: Run Implementation - 2026.1 English

With synthesis completed, you are now ready to script implementation. There are many steps to implementation, in both Project Mode and Non-Project Mode. However, in Project Mode, you select a design run strategy that controls all of the various steps, and launch that run. In Non- Project Mode, without a design run, you must determine your implementation strategy by manually running each step of implementation, and selecting the Tcl command options to use at each step. You can also choose to skip some steps, such as logic optimization, power optimization, and physical synthesis.

In this lab, you run the following steps:

Logic optimization: opt_design
Placement: place_design
Physical synthesis: phys_opt_design
Routing: route_design
Bitstream generation: write_bitstream

For a complete description of each of these steps, refer to the Vivado Design Suite User Guide: Implementation (UG904).

Between each of these steps, you can generate reports, and write checkpoints to save the design in different stages of implementation.

Before you launch the implementation, read the design constraints that are exclusively used in implementation. The XDC file, top_physical.xdc, contains physical constraints that are used in implementation but are not applicable to synthesis.

In this case, you can read these constraints into the in-memory design prior to synthesis because synthesis ignores them. However, this file might also contain different timing constraints that are not used in synthesis, and you must read them in after synthesis and before implementation.

Add the following line to your Tcl script:

read_xdc ../Lab_3_4_sources/Constraints/top_physical.xdc

Add optimization and placement commands to your Tcl script:
```
opt_design
place_design
write_checkpoint -force post_place.dcp
report_timing -file timing_place.rpt
```
After placement completes, your script writes a post-placement checkpoint. It then creates a custom timing report, which provides a detailed timing report for the single worst timing path in the design.
Add physical synthesis and routing commands to your Tcl script:
```
phys_opt_design
route_design
write_checkpoint -force post_route.dcp
report_timing_summary -file timing_summary
```
After routing completes, your script writes a post-routing design checkpoint and creates a timing summary report.
Finally, you can write out a bitstream by adding the following command:
```
write_bitstream -force sys_integration_top.bit
```

This is the complete Non-Project Mode design flow for implementing a design from RTL source files, including designing with IP, through bitstream generation.

Step 7: Run Implementation - Step 7: Run Implementation - 2026.1 English - UG939

Vivado Design Suite Tutorial: Designing with IP (UG939)